Pins

General Description

Definitions for the pinout for each supported device.

Data Structures
struct	cyhal_resource_pin_mapping_t
	Represents an association between a pin and a resource. More...

Typedefs
typedef uint8_t	cyhal_pinmux_t
	Pin mux connections. More...
typedef cyhal_pinmux_t	en_hsiom_sel_t
	Map for compatibility with PSoC drivers.

Enumerations
enum	cyhal_gpio_cluster_t {   CYHAL_GPIO_CLUSTER_BTSS = 0 ,   CYHAL_GPIO_CLUSTER_CTSS = 1 ,   CYHAL_GPIO_CLUSTER_WLSS = 2 }
	Definitions for all of the pins clusters. More...
enum	cyhal_gpio_t {   NC = 0xFF ,   HSIOM_SEL_GPIO = NC ,   BT_GPIO_BASE = 0u ,   BT_GPIO_0 = 0u ,   BT_GPIO_2 = 1u ,   BT_GPIO_3 = 2u ,   BT_GPIO_4 = 3u ,   BT_GPIO_5 = 4u ,   BT_GPIO_6 = 5u ,   BT_GPIO_7 = 6u ,   BT_GPIO_8 = 7u ,   BT_GPIO_9 = 8u ,   BT_GPIO_10 = 9u ,   BT_GPIO_11 = 10u ,   BT_GPIO_12 = 11u ,   BT_GPIO_13 = 12u ,   BT_GPIO_14 = 13u ,   BT_GPIO_15 = 14u ,   BT_GPIO_16 = 15u ,   BT_GPIO_17 = 16u ,   BT_HOST_WAKE = 17u ,   BT_UART_CTS_N = 18u ,   BT_UART_RTS_N = 19u ,   BT_UART_RXD = 20u ,   BT_UART_TXD = 21u ,   DMIC_CK = 22u ,   DMIC_DQ = 23u ,   LHL_GPIO_2 = 24u ,   LHL_GPIO_3 = 25u ,   LHL_GPIO_4 = 26u ,   LHL_GPIO_5 = 27u ,   LHL_GPIO_6 = 28u ,   LHL_GPIO_7 = 29u ,   LHL_GPIO_8 = 30u ,   LHL_GPIO_9 = 31u ,   TDM1_DI = 32u ,   TDM1_DO = 33u ,   TDM1_MCK = 34u ,   TDM1_SCK = 35u ,   TDM1_WS = 36u ,   TDM2_SCK = 37u ,   TDM2_DI = 38u ,   TDM2_MCK = 39u ,   TDM2_DO = 40u ,   TDM2_WS = 41u ,   BT_GPIO_LAST ,   LHL_IO_0 = BT_GPIO_LAST ,   LHL_IO_1 = 43u ,   LHL_IO_2 = 44u ,   LHL_IO_3 = 45u ,   LHL_IO_4 = 46u ,   LHL_IO_5 = 47u ,   LHL_IO_6 = 48u ,   LHL_IO_7 = 49u ,   LHL_IO_8 = 50u ,   LHL_IO_9 = 51u ,   LHL_IO_10 = 52u ,   LHL_IO_I_MIC = 53u ,   CTSS_GPIO_LAST ,   WL_GPIO_0 = CTSS_GPIO_LAST ,   WL_GPIO_2 = 55u ,   WL_GPIO_3 = 56u ,   WL_GPIO_4 = 57u ,   WL_GPIO_5 = 58u ,   WL_GPIO_6 = 59u ,   SDIO_CLK = 60u ,   SDIO_CMD = 61u ,   SDIO_DATA_0 = 62u ,   SDIO_DATA_1 = 63u ,   SDIO_DATA_2 = 64u ,   SDIO_DATA_3 = 65u ,   RFSW_CTRL_0 = 66u ,   RFSW_CTRL_1 = 67u ,   RFSW_CTRL_2 = 68u ,   RFSW_CTRL_3 = 69u ,   RFSW_CTRL_4 = 70u ,   RFSW_CTRL_5 = 71u ,   RFSW_CTRL_6 = 72u ,   RFSW_CTRL_7 = 73u ,   WLSS_GPIO_LAST ,   DIRECT_BASE = WLSS_GPIO_LAST ,   MIC_P = WLSS_GPIO_LAST }
	Definitions for all of the pins that are bonded out on in the package. More...

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Data Structure Documentation

cyhal_resource_pin_mapping_t

struct cyhal_resource_pin_mapping_t

Data Fields
uint8_t	block_num	The associated resource block number.
uint8_t	channel_num	The associated resource block's channel number.
cyhal_gpio_t	pin	The GPIO pin.
cyhal_pinmux_t	functionality	Purpose of the pin.

Typedef Documentation

cyhal_pinmux_t

typedef uint8_t cyhal_pinmux_t

Pin mux connections.

Type is void to include BTSS, CTSS and WLSS data types

Enumeration Type Documentation

cyhal_gpio_cluster_t

enum cyhal_gpio_cluster_t

Definitions for all of the pins clusters.

Enumerator
CYHAL_GPIO_CLUSTER_BTSS	BTSS cluster.
CYHAL_GPIO_CLUSTER_CTSS	CTSS cluster.
CYHAL_GPIO_CLUSTER_WLSS	WLSS cluster.

cyhal_gpio_t

enum cyhal_gpio_t

Definitions for all of the pins that are bonded out on in the package.

Enumerator
NC	No Connect/Invalid Pin.
HSIOM_SEL_GPIO	BWC with PSoC for LPM transitions.
BT_GPIO_BASE	Start of reconfigurable pins.
BT_GPIO_0	BT General Purpose I/O 0.
BT_GPIO_2	BT General Purpose I/O 2.
BT_GPIO_3	BT General Purpose I/O 3.
BT_GPIO_4	BT General Purpose I/O 4.
BT_GPIO_5	BT General Purpose I/O 5.
BT_GPIO_6	BT General Purpose I/O 6.
BT_GPIO_7	BT General Purpose I/O 7.
BT_GPIO_8	BT General Purpose I/O 8.
BT_GPIO_9	BT General Purpose I/O 9.
BT_GPIO_10	BT General Purpose I/O 10.
BT_GPIO_11	BT General Purpose I/O 11.
BT_GPIO_12	BT General Purpose I/O 12.
BT_GPIO_13	BT General Purpose I/O 13.
BT_GPIO_14	BT General Purpose I/O 14.
BT_GPIO_15	BT General Purpose I/O 15.
BT_GPIO_16	BT General Purpose I/O 16.
BT_GPIO_17	BT General Purpose I/O 17.
BT_HOST_WAKE	BT Host Wake.
BT_UART_CTS_N	UART clear-to-send (active-low)
BT_UART_RTS_N	UART request-to-send (active-low)
BT_UART_RXD	UART serial data input.
BT_UART_TXD	UART serial data output.
DMIC_CK	Digital Mic Clock.
DMIC_DQ	Digital Mic Data.
LHL_GPIO_2	LHL General Purpose I/O 2.
LHL_GPIO_3	LHL General Purpose I/O 3.
LHL_GPIO_4	LHL General Purpose I/O 4.
LHL_GPIO_5	LHL General Purpose I/O 5.
LHL_GPIO_6	LHL General Purpose I/O 6.
LHL_GPIO_7	LHL General Purpose I/O 7.
LHL_GPIO_8	LHL General Purpose I/O 8.
LHL_GPIO_9	LHL General Purpose I/O 9.
TDM1_DI	TDM1 Data Input.
TDM1_DO	TDM1 Data Output.
TDM1_MCK	TDM1 Master Clock.
TDM1_SCK	TDM1 Slave Clock.
TDM1_WS	TDM1 WS.
TDM2_SCK	TDM2 Slave Clock.
TDM2_DI	TDM2 Data Input.
TDM2_MCK	TDM1 Master Clock.
TDM2_DO	TDM1 Data Output.
TDM2_WS	TDM2 WS.
BT_GPIO_LAST	End of reconfigurable pins.
LHL_IO_0	LHL General Purpose I/O 0.
LHL_IO_1	LHL I/O 1.
LHL_IO_2	LHL I/O 2.
LHL_IO_3	LHL I/O 3.
LHL_IO_4	LHL I/O 4.
LHL_IO_5	LHL I/O 5.
LHL_IO_6	LHL I/O 6.
LHL_IO_7	LHL I/O 7.
LHL_IO_8	LHL I/O 8.
LHL_IO_9	LHL I/O 9.
LHL_IO_10	LHL I/O 10.
LHL_IO_I_MIC	LHL Input MIC.
CTSS_GPIO_LAST	End of reconfigurable pins.
WL_GPIO_0	WLAN General Purpose I/O 0.
WL_GPIO_2	WLAN General Purpose I/O 0.
WL_GPIO_3	WLAN General Purpose I/O 0.
WL_GPIO_4	WLAN General Purpose I/O 0.
WL_GPIO_5	WLAN General Purpose I/O 0.
WL_GPIO_6	WLAN General Purpose I/O 0.
SDIO_CLK	SDIO Clock I/O.
SDIO_CMD	SDIO Command I/O.
SDIO_DATA_0	SDIO Data 0 I/O.
SDIO_DATA_1	SDIO Data 1 I/O.
SDIO_DATA_2	SDIO Data 2 I/O.
SDIO_DATA_3	SDIO Data 3 I/O.
DIRECT_BASE	Start of direct connection pins.
MIC_P	External Microphone.