PSoC4100Sp 64-QFN

General Description

Pin definitions and connections specific to the PSoC4100Sp 64-QFN package.

Data Structures
struct	cyhal_resource_pin_mapping_t
	Represents an association between a pin and a resource. More...

Macros
#define	CYHAL_GET_GPIO(port, pin)   ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin)))
	Gets a pin definition from the provided port and pin numbers.
#define	CYHAL_GET_PIN(pin)   ((uint8_t)(((uint8_t)pin) & 0x07U))
	Macro that, given a gpio, will extract the pin number.
#define	CYHAL_GET_PORT(pin)   ((uint8_t)((((uint8_t)pin) >> 3U) & 0x1FU))
	Macro that, given a gpio, will extract the port number.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CAN_CAN_RX   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for can_can_rx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CAN_CAN_TX   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for can_can_tx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_CAN_CAN_TX_ENB_N   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for can_can_tx_enb_n.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for lpcomp_dsi_comp.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for lpcomp_inn_comp.
#define	CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for lpcomp_inp_comp.
#define	CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for opamp_dsi_ctb_cmp.
#define	CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for opamp_out_10x.
#define	CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for opamp_vin_m.
#define	CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for opamp_vin_p0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P1   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for opamp_vin_p1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_DATA   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_dsi_sar_data.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_DATA_VALID   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_dsi_sar_data_valid.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_SAMPLE_DONE   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_dsi_sar_sample_done.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_VREF0   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for pass_sar_ext_vref0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_VREF1   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for pass_sar_ext_vref1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS   (CY_GPIO_DM_ANALOG)
	Indicates that a pin map exists for pass_sarmux_pads.
#define	CYHAL_PIN_MAP_DRIVE_MODE_PASS_TR_SAR_OUT   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for pass_tr_sar_out.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL   (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_scl.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA   (CY_GPIO_DM_OD_DRIVESLOW)
	Indicates that a pin map exists for scb_i2c_sda.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_clk.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_m_miso.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_mosi.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select2.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_m_select3.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_clk.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_spi_s_miso.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_mosi.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select0.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select1.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select2.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_spi_s_select3.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_cts.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_rts.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for scb_uart_rx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for scb_uart_tx.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL   (CY_GPIO_DM_STRONG_IN_OFF)
	Indicates that a pin map exists for tcpwm_line_compl.
#define	CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_IN   (CY_GPIO_DM_HIGHZ)
	Indicates that a pin map exists for tcpwm_tr_in.

Typedefs
typedef cyhal_gpio_psoc4100sp_64_qfn_t	cyhal_gpio_t
	Create generic name for the series/package specific type. More...

Enumerations
enum	cyhal_gpio_psoc4100sp_64_qfn_t {   NC = 0xFF,   P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),   P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),   P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),   P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),   P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),   P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),   P0_6 = CYHAL_GET_GPIO(CYHAL_PORT_0, 6),   P0_7 = CYHAL_GET_GPIO(CYHAL_PORT_0, 7),   P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),   P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),   P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),   P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),   P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),   P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),   P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6),   P1_7 = CYHAL_GET_GPIO(CYHAL_PORT_1, 7),   P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),   P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),   P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),   P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),   P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),   P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),   P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),   P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),   P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),   P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),   P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),   P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),   P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),   P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),   P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6),   P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7),   P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),   P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),   P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2),   P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3),   P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4),   P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5),   P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6),   P4_7 = CYHAL_GET_GPIO(CYHAL_PORT_4, 7),   P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),   P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),   P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),   P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),   P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),   P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),   P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),   P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),   P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),   P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),   P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),   P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),   P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),   P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1) }
	Definitions for all of the pins that are bonded out on in the 64-QFN package for the PSoC4100Sp series. More...

Variables
const cyhal_resource_pin_mapping_t	cyhal_pin_map_can_can_rx [2]
	List of valid pin to peripheral connections for the can_can_rx signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_can_can_tx [2]
	List of valid pin to peripheral connections for the can_can_tx signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_can_can_tx_enb_n [2]
	List of valid pin to peripheral connections for the can_can_tx_enb_n signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lpcomp_dsi_comp [6]
	List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lpcomp_inn_comp [2]
	List of valid pin to peripheral connections for the lpcomp_inn_comp signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_lpcomp_inp_comp [2]
	List of valid pin to peripheral connections for the lpcomp_inp_comp signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_opamp_dsi_ctb_cmp [2]
	List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_opamp_out_10x [2]
	List of valid pin to peripheral connections for the opamp_out_10x signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_opamp_vin_m [2]
	List of valid pin to peripheral connections for the opamp_vin_m signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_opamp_vin_p0 [2]
	List of valid pin to peripheral connections for the opamp_vin_p0 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_opamp_vin_p1 [2]
	List of valid pin to peripheral connections for the opamp_vin_p1 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_dsi_sar_data [12]
	List of valid pin to peripheral connections for the pass_dsi_sar_data signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_dsi_sar_data_valid [1]
	List of valid pin to peripheral connections for the pass_dsi_sar_data_valid signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_dsi_sar_sample_done [1]
	List of valid pin to peripheral connections for the pass_dsi_sar_sample_done signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sar_ext_vref0 [1]
	List of valid pin to peripheral connections for the pass_sar_ext_vref0 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sar_ext_vref1 [1]
	List of valid pin to peripheral connections for the pass_sar_ext_vref1 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_sarmux_pads [8]
	List of valid pin to peripheral connections for the pass_sarmux_pads signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_pass_tr_sar_out [1]
	List of valid pin to peripheral connections for the pass_tr_sar_out signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_scl [12]
	List of valid pin to peripheral connections for the scb_i2c_scl signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_i2c_sda [12]
	List of valid pin to peripheral connections for the scb_i2c_sda signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_clk [9]
	List of valid pin to peripheral connections for the scb_spi_m_clk signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_miso [10]
	List of valid pin to peripheral connections for the scb_spi_m_miso signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_mosi [10]
	List of valid pin to peripheral connections for the scb_spi_m_mosi signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select0 [8]
	List of valid pin to peripheral connections for the scb_spi_m_select0 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select1 [7]
	List of valid pin to peripheral connections for the scb_spi_m_select1 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select2 [8]
	List of valid pin to peripheral connections for the scb_spi_m_select2 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_m_select3 [7]
	List of valid pin to peripheral connections for the scb_spi_m_select3 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_clk [9]
	List of valid pin to peripheral connections for the scb_spi_s_clk signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_miso [10]
	List of valid pin to peripheral connections for the scb_spi_s_miso signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_mosi [10]
	List of valid pin to peripheral connections for the scb_spi_s_mosi signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select0 [8]
	List of valid pin to peripheral connections for the scb_spi_s_select0 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select1 [7]
	List of valid pin to peripheral connections for the scb_spi_s_select1 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select2 [8]
	List of valid pin to peripheral connections for the scb_spi_s_select2 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_spi_s_select3 [7]
	List of valid pin to peripheral connections for the scb_spi_s_select3 signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_cts [9]
	List of valid pin to peripheral connections for the scb_uart_cts signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rts [8]
	List of valid pin to peripheral connections for the scb_uart_rts signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_rx [10]
	List of valid pin to peripheral connections for the scb_uart_rx signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_scb_uart_tx [11]
	List of valid pin to peripheral connections for the scb_uart_tx signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line [20]
	List of valid pin to peripheral connections for the tcpwm_line signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_line_compl [19]
	List of valid pin to peripheral connections for the tcpwm_line_compl signal. More...
const cyhal_resource_pin_mapping_t	cyhal_pin_map_tcpwm_tr_in [7]
	List of valid pin to peripheral connections for the tcpwm_tr_in signal. More...

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Data Structure Documentation

cyhal_resource_pin_mapping_t

struct cyhal_resource_pin_mapping_t

Data Fields
uint8_t	block_num	The block number of the resource with this connection.
uint8_t	channel_num	The channel number of the block with this connection.
cyhal_gpio_t	pin	The GPIO pin the connection is with.
en_hsiom_sel_t	hsiom	The HSIOM configuration value.

Typedef Documentation

cyhal_gpio_t

typedef cyhal_gpio_psoc4100sp_64_qfn_t cyhal_gpio_t

Create generic name for the series/package specific type.

Enumeration Type Documentation

cyhal_gpio_psoc4100sp_64_qfn_t

enum cyhal_gpio_psoc4100sp_64_qfn_t

Definitions for all of the pins that are bonded out on in the 64-QFN package for the PSoC4100Sp series.

Enumerator
NC	No Connect/Invalid Pin.
P0_0	Port 0 Pin 0.
P0_1	Port 0 Pin 1.
P0_2	Port 0 Pin 2.
P0_3	Port 0 Pin 3.
P0_4	Port 0 Pin 4.
P0_5	Port 0 Pin 5.
P0_6	Port 0 Pin 6.
P0_7	Port 0 Pin 7.
P1_0	Port 1 Pin 0.
P1_1	Port 1 Pin 1.
P1_2	Port 1 Pin 2.
P1_3	Port 1 Pin 3.
P1_4	Port 1 Pin 4.
P1_5	Port 1 Pin 5.
P1_6	Port 1 Pin 6.
P1_7	Port 1 Pin 7.
P2_0	Port 2 Pin 0.
P2_1	Port 2 Pin 1.
P2_2	Port 2 Pin 2.
P2_3	Port 2 Pin 3.
P2_4	Port 2 Pin 4.
P2_5	Port 2 Pin 5.
P2_6	Port 2 Pin 6.
P2_7	Port 2 Pin 7.
P3_0	Port 3 Pin 0.
P3_1	Port 3 Pin 1.
P3_2	Port 3 Pin 2.
P3_3	Port 3 Pin 3.
P3_4	Port 3 Pin 4.
P3_5	Port 3 Pin 5.
P3_6	Port 3 Pin 6.
P3_7	Port 3 Pin 7.
P4_0	Port 4 Pin 0.
P4_1	Port 4 Pin 1.
P4_2	Port 4 Pin 2.
P4_3	Port 4 Pin 3.
P4_4	Port 4 Pin 4.
P4_5	Port 4 Pin 5.
P4_6	Port 4 Pin 6.
P4_7	Port 4 Pin 7.
P5_0	Port 5 Pin 0.
P5_1	Port 5 Pin 1.
P5_2	Port 5 Pin 2.
P5_3	Port 5 Pin 3.
P5_5	Port 5 Pin 5.
P5_6	Port 5 Pin 6.
P5_7	Port 5 Pin 7.
P6_0	Port 6 Pin 0.
P6_1	Port 6 Pin 1.
P6_2	Port 6 Pin 2.
P6_4	Port 6 Pin 4.
P6_5	Port 6 Pin 5.
P7_0	Port 7 Pin 0.
P7_1	Port 7 Pin 1.

Variable Documentation

cyhal_pin_map_can_can_rx

const cyhal_resource_pin_mapping_t cyhal_pin_map_can_can_rx[2]

List of valid pin to peripheral connections for the can_can_rx signal.

cyhal_pin_map_can_can_tx

const cyhal_resource_pin_mapping_t cyhal_pin_map_can_can_tx[2]

List of valid pin to peripheral connections for the can_can_tx signal.

cyhal_pin_map_can_can_tx_enb_n

const cyhal_resource_pin_mapping_t cyhal_pin_map_can_can_tx_enb_n[2]

List of valid pin to peripheral connections for the can_can_tx_enb_n signal.

cyhal_pin_map_lpcomp_dsi_comp

const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[6]

List of valid pin to peripheral connections for the lpcomp_dsi_comp signal.

cyhal_pin_map_lpcomp_inn_comp

const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]

List of valid pin to peripheral connections for the lpcomp_inn_comp signal.

cyhal_pin_map_lpcomp_inp_comp

const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]

List of valid pin to peripheral connections for the lpcomp_inp_comp signal.

cyhal_pin_map_opamp_dsi_ctb_cmp

const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]

List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal.

cyhal_pin_map_opamp_out_10x

const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]

List of valid pin to peripheral connections for the opamp_out_10x signal.

cyhal_pin_map_opamp_vin_m

const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]

List of valid pin to peripheral connections for the opamp_vin_m signal.

cyhal_pin_map_opamp_vin_p0

const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]

List of valid pin to peripheral connections for the opamp_vin_p0 signal.

cyhal_pin_map_opamp_vin_p1

const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2]

List of valid pin to peripheral connections for the opamp_vin_p1 signal.

cyhal_pin_map_pass_dsi_sar_data

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_data[12]

List of valid pin to peripheral connections for the pass_dsi_sar_data signal.

cyhal_pin_map_pass_dsi_sar_data_valid

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_data_valid[1]

List of valid pin to peripheral connections for the pass_dsi_sar_data_valid signal.

cyhal_pin_map_pass_dsi_sar_sample_done

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_sample_done[1]

List of valid pin to peripheral connections for the pass_dsi_sar_sample_done signal.

cyhal_pin_map_pass_sar_ext_vref0

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_vref0[1]

List of valid pin to peripheral connections for the pass_sar_ext_vref0 signal.

cyhal_pin_map_pass_sar_ext_vref1

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_vref1[1]

List of valid pin to peripheral connections for the pass_sar_ext_vref1 signal.

cyhal_pin_map_pass_sarmux_pads

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]

List of valid pin to peripheral connections for the pass_sarmux_pads signal.

cyhal_pin_map_pass_tr_sar_out

const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_tr_sar_out[1]

List of valid pin to peripheral connections for the pass_tr_sar_out signal.

cyhal_pin_map_scb_i2c_scl

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]

List of valid pin to peripheral connections for the scb_i2c_scl signal.

cyhal_pin_map_scb_i2c_sda

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]

List of valid pin to peripheral connections for the scb_i2c_sda signal.

cyhal_pin_map_scb_spi_m_clk

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]

List of valid pin to peripheral connections for the scb_spi_m_clk signal.

cyhal_pin_map_scb_spi_m_miso

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10]

List of valid pin to peripheral connections for the scb_spi_m_miso signal.

cyhal_pin_map_scb_spi_m_mosi

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10]

List of valid pin to peripheral connections for the scb_spi_m_mosi signal.

cyhal_pin_map_scb_spi_m_select0

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]

List of valid pin to peripheral connections for the scb_spi_m_select0 signal.

cyhal_pin_map_scb_spi_m_select1

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[7]

List of valid pin to peripheral connections for the scb_spi_m_select1 signal.

cyhal_pin_map_scb_spi_m_select2

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]

List of valid pin to peripheral connections for the scb_spi_m_select2 signal.

cyhal_pin_map_scb_spi_m_select3

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7]

List of valid pin to peripheral connections for the scb_spi_m_select3 signal.

cyhal_pin_map_scb_spi_s_clk

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]

List of valid pin to peripheral connections for the scb_spi_s_clk signal.

cyhal_pin_map_scb_spi_s_miso

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10]

List of valid pin to peripheral connections for the scb_spi_s_miso signal.

cyhal_pin_map_scb_spi_s_mosi

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10]

List of valid pin to peripheral connections for the scb_spi_s_mosi signal.

cyhal_pin_map_scb_spi_s_select0

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]

List of valid pin to peripheral connections for the scb_spi_s_select0 signal.

cyhal_pin_map_scb_spi_s_select1

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[7]

List of valid pin to peripheral connections for the scb_spi_s_select1 signal.

cyhal_pin_map_scb_spi_s_select2

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]

List of valid pin to peripheral connections for the scb_spi_s_select2 signal.

cyhal_pin_map_scb_spi_s_select3

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7]

List of valid pin to peripheral connections for the scb_spi_s_select3 signal.

cyhal_pin_map_scb_uart_cts

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9]

List of valid pin to peripheral connections for the scb_uart_cts signal.

cyhal_pin_map_scb_uart_rts

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8]

List of valid pin to peripheral connections for the scb_uart_rts signal.

cyhal_pin_map_scb_uart_rx

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10]

List of valid pin to peripheral connections for the scb_uart_rx signal.

cyhal_pin_map_scb_uart_tx

const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]

List of valid pin to peripheral connections for the scb_uart_tx signal.

cyhal_pin_map_tcpwm_line

const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[20]

List of valid pin to peripheral connections for the tcpwm_line signal.

cyhal_pin_map_tcpwm_line_compl

const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[19]

List of valid pin to peripheral connections for the tcpwm_line_compl signal.

cyhal_pin_map_tcpwm_tr_in

const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_in[7]

List of valid pin to peripheral connections for the tcpwm_tr_in signal.