Description

Serial Memory Interface (SMIF_CACHE_BLOCK)

Data Fields
__IM uint32_t	HWPARAMS

__IM uint32_t	RESERVED [3]

__IOM uint32_t	CTRL

__IM uint32_t	NSEC_ACCESS

__IM uint32_t	RESERVED1 [2]

__OM uint32_t	MAINT_CTRL_ALL

__OM uint32_t	MAINT_CTRL_LINES

__IM uint32_t	MAINT_STATUS

__IM uint32_t	RESERVED2 [53]

__IM uint32_t	SECIRQSTAT

__OM uint32_t	SECIRQSCLR

__IOM uint32_t	SECIRQEN

__IM uint32_t	SECIRQINFO1

__IM uint32_t	SECIRQINFO2

__IM uint32_t	RESERVED3 [11]

__IM uint32_t	NSECIRQSTAT

__OM uint32_t	NSECIRQSCLR

__IOM uint32_t	NSECIRQEN

__IM uint32_t	NSECIRQINFO1

__IM uint32_t	NSECIRQINFO2

__IM uint32_t	RESERVED4 [107]

__IM uint32_t	SECHIT

__IM uint32_t	SECMISS

__IOM uint32_t	SECSTATCTRL

__IM uint32_t	RESERVED5

__IM uint32_t	NSECHIT

__IM uint32_t	NSECMISS

__IOM uint32_t	NSECSTATCTRL

__IM uint32_t	RESERVED6 [185]

__IM uint32_t	PMSVR0

__IM uint32_t	PMSVR1

__IM uint32_t	PMSVR2

__IM uint32_t	PMSVR3

__IM uint32_t	RESERVED7 [28]

__IM uint32_t	PMSSSR

__IM uint32_t	RESERVED8 [27]

__OM uint32_t	PMSSCR

__IOM uint32_t	PMSSRR

__IM uint32_t	RESERVED9 [566]

__IM uint32_t	PIDR4

__IM uint32_t	PIDR5

__IM uint32_t	PIDR6

__IM uint32_t	PIDR7

__IM uint32_t	PIDR0

__IM uint32_t	PIDR1

__IM uint32_t	PIDR2

__IM uint32_t	PIDR3

__IM uint32_t	CIDR0

__IM uint32_t	CIDR1

__IM uint32_t	CIDR2

__IM uint32_t	CIDR3

__IM uint32_t	RESERVED10 [1024]

SMIF_CACHE_BLOCK_MMIO_Type	MMIO

__IM uint32_t	RESERVED11 [2016]

SMIF_CACHE_BLOCK_CACHEBLK_AHB_Type	CACHEBLK_AHB

__IM uint32_t	RESERVED12 [11264]

Field Documentation

◆ HWPARAMS

__IM uint32_t SMIF_CACHE_BLOCK_Type::HWPARAMS

0x00000000 Hardware Parameter register

◆ RESERVED

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED[3]

◆ CTRL

__IOM uint32_t SMIF_CACHE_BLOCK_Type::CTRL

0x00000010 Control Register

◆ NSEC_ACCESS

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSEC_ACCESS

0x00000014 Non-secure access information

◆ RESERVED1

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED1[2]

◆ MAINT_CTRL_ALL

__OM uint32_t SMIF_CACHE_BLOCK_Type::MAINT_CTRL_ALL

0x00000020 Maintenance control for the entire cache

◆ MAINT_CTRL_LINES

__OM uint32_t SMIF_CACHE_BLOCK_Type::MAINT_CTRL_LINES

0x00000024 Maintenance control for individual lines

◆ MAINT_STATUS

__IM uint32_t SMIF_CACHE_BLOCK_Type::MAINT_STATUS

0x00000028 Maintenance status for the cache

◆ RESERVED2

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED2[53]

◆ SECIRQSTAT

__IM uint32_t SMIF_CACHE_BLOCK_Type::SECIRQSTAT

0x00000100 Secure Interrupt Request Status register

◆ SECIRQSCLR

__OM uint32_t SMIF_CACHE_BLOCK_Type::SECIRQSCLR

0x00000104 Secure Interrupt Status Clear register

◆ SECIRQEN

__IOM uint32_t SMIF_CACHE_BLOCK_Type::SECIRQEN

0x00000108 Secure Interrupt Enable register

◆ SECIRQINFO1

__IM uint32_t SMIF_CACHE_BLOCK_Type::SECIRQINFO1

0x0000010C Secure transfer error information 1

◆ SECIRQINFO2

__IM uint32_t SMIF_CACHE_BLOCK_Type::SECIRQINFO2

0x00000110 Secure transfer error information 2

◆ RESERVED3

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED3[11]

◆ NSECIRQSTAT

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSECIRQSTAT

0x00000140 Non-secure Interrupt Request Status register

◆ NSECIRQSCLR

__OM uint32_t SMIF_CACHE_BLOCK_Type::NSECIRQSCLR

0x00000144 Non-secure Interrupt Status Clear register

◆ NSECIRQEN

__IOM uint32_t SMIF_CACHE_BLOCK_Type::NSECIRQEN

0x00000148 Non-secure Interrupt Enable register

◆ NSECIRQINFO1

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSECIRQINFO1

0x0000014C Non-secure transfer error information 1

◆ NSECIRQINFO2

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSECIRQINFO2

0x00000150 Non-secure transfer error information 2

◆ RESERVED4

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED4[107]

◆ SECHIT

__IM uint32_t SMIF_CACHE_BLOCK_Type::SECHIT

0x00000300 Secure transfers Hit register

◆ SECMISS

__IM uint32_t SMIF_CACHE_BLOCK_Type::SECMISS

0x00000304 Secure transfers Miss register

◆ SECSTATCTRL

__IOM uint32_t SMIF_CACHE_BLOCK_Type::SECSTATCTRL

0x00000308 Secure transfers statistic counters control

◆ RESERVED5

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED5

◆ NSECHIT

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSECHIT

0x00000310 Non-secure transfers Hit register

◆ NSECMISS

__IM uint32_t SMIF_CACHE_BLOCK_Type::NSECMISS

0x00000314 Non-secure transfers Miss register

◆ NSECSTATCTRL

__IOM uint32_t SMIF_CACHE_BLOCK_Type::NSECSTATCTRL

0x00000318 Non-secure transfers statistic counters control

◆ RESERVED6

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED6[185]

◆ PMSVR0

__IM uint32_t SMIF_CACHE_BLOCK_Type::PMSVR0

0x00000600 Saved Value Register 0 - Secure Hit

◆ PMSVR1

__IM uint32_t SMIF_CACHE_BLOCK_Type::PMSVR1

0x00000604 Saved Value Register 1 - Secure Miss

◆ PMSVR2

__IM uint32_t SMIF_CACHE_BLOCK_Type::PMSVR2

0x00000608 Saved Value Register 2 - Non-secure Hit

◆ PMSVR3

__IM uint32_t SMIF_CACHE_BLOCK_Type::PMSVR3

0x0000060C Saved Value Register 3 - Non-secure Miss

◆ RESERVED7

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED7[28]

◆ PMSSSR

__IM uint32_t SMIF_CACHE_BLOCK_Type::PMSSSR

0x00000680 PMU Snapshot Status Register

◆ RESERVED8

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED8[27]

◆ PMSSCR

__OM uint32_t SMIF_CACHE_BLOCK_Type::PMSSCR

0x000006F0 PMU Snapshot Capture Register

◆ PMSSRR

__IOM uint32_t SMIF_CACHE_BLOCK_Type::PMSSRR

0x000006F4 PMU Snapshot Reset Register

◆ RESERVED9

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED9[566]

◆ PIDR4

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR4

0x00000FD0 Peripheral ID 4

◆ PIDR5

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR5

0x00000FD4 Peripheral ID 5

◆ PIDR6

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR6

0x00000FD8 Peripheral ID 6

◆ PIDR7

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR7

0x00000FDC Peripheral ID 7

◆ PIDR0

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR0

0x00000FE0 Peripheral ID 0

◆ PIDR1

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR1

0x00000FE4 Peripheral ID 1

◆ PIDR2

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR2

0x00000FE8 Peripheral ID 2

◆ PIDR3

__IM uint32_t SMIF_CACHE_BLOCK_Type::PIDR3

0x00000FEC Peripheral ID 3

◆ CIDR0

__IM uint32_t SMIF_CACHE_BLOCK_Type::CIDR0

0x00000FF0 Component ID 0

◆ CIDR1

__IM uint32_t SMIF_CACHE_BLOCK_Type::CIDR1

0x00000FF4 Component ID 1

◆ CIDR2

__IM uint32_t SMIF_CACHE_BLOCK_Type::CIDR2

0x00000FF8 Component ID 2

◆ CIDR3

__IM uint32_t SMIF_CACHE_BLOCK_Type::CIDR3

0x00000FFC Component ID 3

◆ RESERVED10

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED10[1024]

◆ MMIO

SMIF_CACHE_BLOCK_MMIO_Type SMIF_CACHE_BLOCK_Type::MMIO

0x00002000 MMIO regs for cacheblock (anything other than cache IP related MMIO regs)

◆ RESERVED11

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED11[2016]

◆ CACHEBLK_AHB

SMIF_CACHE_BLOCK_CACHEBLK_AHB_Type SMIF_CACHE_BLOCK_Type::CACHEBLK_AHB

0x00004000 SMIF Cacheblock MPC

◆ RESERVED12

__IM uint32_t SMIF_CACHE_BLOCK_Type::RESERVED12[11264]