Description

MMIO regs for cacheblock (anything other than cache IP related MMIO regs) (SMIF_CACHE_BLOCK_MMIO)

Data Fields
__IOM uint32_t	BYPASS_WI

__IOM uint32_t	MASTER_ID

__IOM uint32_t	DIS_CACHE_EN_MAINT

__IOM uint32_t	DIS_CACHE_DIS_MAINT

__IOM uint32_t	APB_VIOLATION_RESP

__IOM uint32_t	MMIO_ACTIVE_EN

__IOM uint32_t	POWER_ON_ENABLE

__IOM uint32_t	MMIO_CACHE_RET_EN

__IOM uint32_t	DIS_PWR_DOWN_MAINT

__IOM uint32_t	REGION0_BASE

__IOM uint32_t	REGION0_LIMIT

__IOM uint32_t	REGION1_BASE

__IOM uint32_t	REGION1_LIMIT

__IOM uint32_t	REGION2_BASE

__IOM uint32_t	REGION2_LIMIT

__IOM uint32_t	REGION3_BASE

__IOM uint32_t	REGION3_LIMIT

__IM uint32_t	RESERVED [15]

Field Documentation

◆ BYPASS_WI

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::BYPASS_WI

0x00000000 Bypass wrap to increment conversion logic

◆ MASTER_ID

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::MASTER_ID

0x00000004 The cache generates transactions (linefill and eviction Write-Back) that are marked with the value specified by MASTER_ID on hmaster_m.

◆ DIS_CACHE_EN_MAINT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::DIS_CACHE_EN_MAINT

0x00000008 This signal turns on/off cache enable maintenance.

◆ DIS_CACHE_DIS_MAINT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::DIS_CACHE_DIS_MAINT

0x0000000C This signal turns on/off cache disable maintenance.

◆ APB_VIOLATION_RESP

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::APB_VIOLATION_RESP

0x00000010 This signal controls if the APB interface of cache responds with an error to illegal operations on the APB interface. Illegal operations on the APB interface include Writing with no full write strobe, Accessing non-word aligned addresses, Instruction accesses, Non-privileged accesses 1 - The Cache responds with an APB error. Read data is masked with zeros and write data is ignored. 0 - The Cache sends an OK response. Read data is masked with zeros and write data is ignored.

◆ MMIO_ACTIVE_EN

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::MMIO_ACTIVE_EN

0x00000014 SW control to put SMIF.6 in active or clock gated mode

◆ POWER_ON_ENABLE

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::POWER_ON_ENABLE

0x00000018 This signal configures the cache to enable the cache automatically after powerup.

◆ MMIO_CACHE_RET_EN

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::MMIO_CACHE_RET_EN

0x0000001C Controls if cache SRAMs are retained during DPSLP

◆ DIS_PWR_DOWN_MAINT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::DIS_PWR_DOWN_MAINT

0x00000020 This signal turns on/off powerdown maintenance.

◆ REGION0_BASE

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION0_BASE

0x00000024 Region 0 Attributes - register 0; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION0_LIMIT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION0_LIMIT

0x00000028 Region 0 Attributes - register 1; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION1_BASE

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION1_BASE

0x0000002C Region 1 Attributes - register 0; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION1_LIMIT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION1_LIMIT

0x00000030 Region 1 Attributes - register 1; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION2_BASE

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION2_BASE

0x00000034 Region 2 Attributes - register 0; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION2_LIMIT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION2_LIMIT

0x00000038 Region 2 Attributes - register 1; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION3_BASE

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION3_BASE

0x0000003C Region 3 Attributes - register 0; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ REGION3_LIMIT

__IOM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::REGION3_LIMIT

0x00000040 Region 3 Attributes - register 1; Region attributes shall be changed exclusively while the SMIF is disabled, and the XIP interfaces are idle

◆ RESERVED

__IM uint32_t SMIF_CACHE_BLOCK_MMIO_Type::RESERVED[15]