The Power Mode Status Defines

General Description

Defines for the CPU and system power modes status.

Macros
#define	CY_SYSPM_STATUS_CM33_ACTIVE   ((uint32_t) ((uint32_t)0x1U << 16U))
	The CM33 is Active.
#define	CY_SYSPM_STATUS_CM33_SLEEP   ((uint32_t) ((uint32_t)0x2U << 16U))
	The CM33 is in Sleep.
#define	CY_SYSPM_STATUS_CM33_DEEPSLEEP   ((uint32_t) ((uint32_t)0x4U << 16U))
	The CM33 is in DeepSleep.
#define	CY_SYSPM_STATUS_CM55_ACTIVE   ((uint32_t) ((uint32_t)0x1U << 20U))
	The CM55 is Active.
#define	CY_SYSPM_STATUS_CM55_SLEEP   ((uint32_t) ((uint32_t)0x2U << 20U))
	The CM55 is in Sleep.
#define	CY_SYSPM_STATUS_CM55_DEEPSLEEP   ((uint32_t) ((uint32_t)0x4U << 20U))
	The CM55 is in DeepSleep.
#define	CY_SYSPM_STATUS_SYSTEM_LP   ((uint32_t) ((uint32_t)0x80U))
	The system is Low Power mode.
#define	CY_SYSPM_STATUS_SYSTEM_ULP   ((uint32_t) ((uint32_t)0x08U << 8U))
	The system is in Ultra Low Power mode.
#define	CY_SYSPM_STATUS_SYSTEM_LPACTIVE   ((uint32_t) ((uint32_t)0x08UL << 16U))
	The system is LPACTIVE Power mode.
#define	CY_SYSPM_STATUS_SYSTEM_HP   ((uint32_t) ((uint32_t)0x08UL << 24U))
	The system is HP Power mode.
#define	CY_SYSPM_STATUS_SYSTEM_OD   ((uint32_t) ((uint32_t)0x08UL << 28U))
	The system is OD Low Power mode.
#define	CY_SYSPM_ACTIVE_TO_LP_WAIT_US   (1u)
	The wait time for transition of the device from the Active into the LPActive (Low Power Active)
#define	CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US   (8u)
	The wait delay time which occurs before the Active reference is settled. More...
#define	CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US   (1u)
	The wait delay time which occurs after the Active reference is settled. More...
#define	CY_SYSPM_WAIT_DELAY_TRIES   (100u)
	The internal define of the tries number in the Cy_SysPm_ExitLpMode() function.

Macro Definition Documentation

CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US

#define CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US   (8u)

The wait delay time which occurs before the Active reference is settled.

This delay is used in transition of the device from Active into the LPACTIVE (Low Power Active) mode

CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US

#define CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US   (1u)

The wait delay time which occurs after the Active reference is settled.

This delay is used in transition the device from Active into the LPACTIVE (Low Power Active) mode