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#define | CY_SYSCLK_DRV_VERSION_MAJOR 3 |
| | Driver major version.
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#define | CY_SYSCLK_DRV_VERSION_MINOR 150 |
| | Driver minor version.
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#define | CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) |
| | Sysclk driver identifier.
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#define | CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */ |
| | ILO clock frequency.
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#define | CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */ |
| | WCO clock frequency.
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#define | CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */ |
| | PILO clock frequency.
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#define | CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */ |
| | IMO clock frequency.
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#define | CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */ |
| | MFO clock frequency.
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#define | CY_SYSCLK_PILO_TRIM_STEP (5UL) /* Default PILO TRIM Step size */ |
| | CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value.
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#define | CY_SYSCLK_IHO_FREQ (50000000UL) /* Hz */ |
| | IHO clock frequency.
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#define | CY_SYSCLK_TIMER_CLK_FREQ (1000000UL) /* Hz */ |
| | Timer clock frequency.
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#define | CY_SYSCLK_BYPASS_CONFIGURE_DELAY (2UL) /* micro seconds */ |
| | FLL BYPASS configure Delay , As per SAS "When changing BYPASS_SEL, do not turn off the reference clock
or CCO clock for ten cycles (whichever is slower)" Slower if IMO, so delay = (10 * 1/(IMO freq in Mhz)) = 1.25 micro seconds, approximated to 2 micro second.
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#define | CY_SYSCLK_FLL_DISABLE_TIMEOUT (100UL) /* micro seconds */ |
| | FLL Disable Timeout value.
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| #define | CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) |
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