PSOC E8XXGP Device Support Library

General Description

Enumerations

enum  cy_en_clkhf_in_sources_t {
  CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14U ,
  CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15U
}
 Selects which clkHf input, or root mux, to configure. More...
 
enum  cy_en_clkhf_dividers_t {
  CY_SYSCLK_CLKHF_NO_DIVIDE = 0U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_3 = 2U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 3U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_5 = 4U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_6 = 5U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_7 = 6U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 7U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_9 = 8U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_10 = 9U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_11 = 10U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_12 = 11U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_13 = 12U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_14 = 13U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_15 = 14U ,
  CY_SYSCLK_CLKHF_DIVIDE_BY_16 = 15U ,
  CY_SYSCLK_CLKHF_MAX_DIVIDER
}
 clkHf divider values. More...
 
enum  cy_en_clkhf_csv_ref_clk_t {
  CY_SYSCLK_CLKHF_CSV_REF_IMO = 0U ,
  CY_SYSCLK_CLKHF_CSV_REF_EXT = 1U ,
  CY_SYSCLK_CLKHF_CSV_REF_ECO = 2U ,
  CY_SYSCLK_CLKHF_CSV_REF_ALTHF0 = 3U ,
  CY_SYSCLK_CLKHF_CSV_REF_IHO = 4U ,
  CY_SYSCLK_CLKHF_CSV_REF_ALTHF1 = 5U
}
 clkhf csv reference clock input sources. More...
 
enum  cy_en_clkhf_csv_action_t {
  CY_SYSCLK_CLKHF_CSV_ACTION_FAULT = 0U ,
  CY_SYSCLK_CLKHF_CSV_ACTION_RESET = 1U
}
 clkhf csv supported action when an anomaly is detected. More...
 

Enumeration Type Documentation

◆ cy_en_clkhf_in_sources_t

Selects which clkHf input, or root mux, to configure.

See CLK_ROOT_SELECT registers, bits ROOT_MUX. Used with functions Cy_SysClk_ClkHfSetSource and Cy_SysClk_ClkHfGetSource.

Enumerator
CY_SYSCLK_CLKHF_IN_CLKPATH0 

clkHf input is Clock Path 0

CY_SYSCLK_CLKHF_IN_CLKPATH1 

clkHf input is Clock Path 1

CY_SYSCLK_CLKHF_IN_CLKPATH2 

clkHf input is Clock Path 2

CY_SYSCLK_CLKHF_IN_CLKPATH3 

clkHf input is Clock Path 3

CY_SYSCLK_CLKHF_IN_CLKPATH4 

clkHf input is Clock Path 4

CY_SYSCLK_CLKHF_IN_CLKPATH5 

clkHf input is Clock Path 5

CY_SYSCLK_CLKHF_IN_CLKPATH6 

clkHf input is Clock Path 6

CY_SYSCLK_CLKHF_IN_CLKPATH7 

clkHf input is Clock Path 7

CY_SYSCLK_CLKHF_IN_CLKPATH8 

clkHf input is Clock Path 8

CY_SYSCLK_CLKHF_IN_CLKPATH9 

clkHf input is Clock Path 9

CY_SYSCLK_CLKHF_IN_CLKPATH10 

clkHf input is Clock Path 10

CY_SYSCLK_CLKHF_IN_CLKPATH11 

clkHf input is Clock Path 11

CY_SYSCLK_CLKHF_IN_CLKPATH12 

clkHf input is Clock Path 12

CY_SYSCLK_CLKHF_IN_CLKPATH13 

clkHf input is Clock Path 13

CY_SYSCLK_CLKHF_IN_CLKPATH14 

clkHf input is Clock Path 14

CY_SYSCLK_CLKHF_IN_CLKPATH15 

clkHf input is Clock Path 15

◆ cy_en_clkhf_dividers_t

clkHf divider values.

See CLK_ROOT_SELECT registers, bits ROOT_DIV. Used with functions Cy_SysClk_ClkHfSetDivider and Cy_SysClk_ClkHfGetDivider.

Enumerator
CY_SYSCLK_CLKHF_NO_DIVIDE 

don't divide clkHf

CY_SYSCLK_CLKHF_DIVIDE_BY_2 

divide clkHf by 2

CY_SYSCLK_CLKHF_DIVIDE_BY_3 

divide clkHf by 3

CY_SYSCLK_CLKHF_DIVIDE_BY_4 

divide clkHf by 4

CY_SYSCLK_CLKHF_DIVIDE_BY_5 

divide clkHf by 5

CY_SYSCLK_CLKHF_DIVIDE_BY_6 

divide clkHf by 6

CY_SYSCLK_CLKHF_DIVIDE_BY_7 

divide clkHf by 7

CY_SYSCLK_CLKHF_DIVIDE_BY_8 

divide clkHf by 8

CY_SYSCLK_CLKHF_DIVIDE_BY_9 

divide clkHf by 9

CY_SYSCLK_CLKHF_DIVIDE_BY_10 

divide clkHf by 10

CY_SYSCLK_CLKHF_DIVIDE_BY_11 

divide clkHf by 11

CY_SYSCLK_CLKHF_DIVIDE_BY_12 

divide clkHf by 12

CY_SYSCLK_CLKHF_DIVIDE_BY_13 

divide clkHf by 13

CY_SYSCLK_CLKHF_DIVIDE_BY_14 

divide clkHf by 14

CY_SYSCLK_CLKHF_DIVIDE_BY_15 

divide clkHf by 15

CY_SYSCLK_CLKHF_DIVIDE_BY_16 

divide clkHf by 16

CY_SYSCLK_CLKHF_MAX_DIVIDER 

Max divider.

◆ cy_en_clkhf_csv_ref_clk_t

clkhf csv reference clock input sources.

See register CSV_REF_SEL

Enumerator
CY_SYSCLK_CLKHF_CSV_REF_IMO 

Reference clock is the IMO.

CY_SYSCLK_CLKHF_CSV_REF_EXT 

Reference clock is the external clock.

CY_SYSCLK_CLKHF_CSV_REF_ECO 

Reference clock is ECO.

CY_SYSCLK_CLKHF_CSV_REF_ALTHF0 

Reference clock is ALTHF0.

CY_SYSCLK_CLKHF_CSV_REF_IHO 

Reference clock is IHO.

CY_SYSCLK_CLKHF_CSV_REF_ALTHF1 

Reference clock is ALTHF1.

◆ cy_en_clkhf_csv_action_t

clkhf csv supported action when an anomaly is detected.

Enumerator
CY_SYSCLK_CLKHF_CSV_ACTION_FAULT 

Generates a fault.

CY_SYSCLK_CLKHF_CSV_ACTION_RESET 

Generates a Reset.