PSOC E8XXGP Device Support Library
Macros | Typedefs
SFDP Macros
PDL API Reference » SMIF (Serial Memory Interface) » Macros

General Description

Macros

#define CY_SMIF_SFDP_ADDRESS_LENGTH   (0x03U)
 The length of the SFDP address.
 
#define CY_SMIF_SFDP_PARAM_HEADER_LENGTH   (0x8U)
 The length of the Parameter header.
 
#define CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH   (0x80U)
 The length of the Parameter table.
 
#define CY_SMIF_SFDP_LENGTH   (CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH)
 The length of the SFDP.
 
#define CY_SMIF_SFDP_SIGNATURE_BYTE_00   (0x00U)
 The SFDP Signature byte 0x00. More...
 
#define CY_SMIF_SFDP_SIGNATURE_BYTE_01   (0x01U)
 The SFDP Signature byte 0x01. More...
 
#define CY_SMIF_SFDP_SIGNATURE_BYTE_02   (0x02U)
 The SFDP Signature byte 0x02. More...
 
#define CY_SMIF_SFDP_SIGNATURE_BYTE_03   (0x03U)
 The SFDP Signature byte 0x03. More...
 
#define CY_SMIF_SFDP_MINOR_REV   (0x04U)
 The SFDP Header byte 0x04. More...
 
#define CY_SMIF_SFDP_MAJOR_REV   (0x05U)
 The SFDP Header byte 0x05. More...
 
#define CY_SMIF_SFDP_MAJOR_REV_1   (0x01U)
 The SFDP Major Revision is 1.
 
#define CY_SMIF_SFDP_JEDEC_REV_0   (0x00U)
 The JEDEC JESD216 Revision is 0.
 
#define CY_SMIF_SFDP_JEDEC_REV_B   (0x06U)
 The JEDEC JESD216 Revision is B.
 
#define CY_SMIF_SFDP_JEDEC_REV_D   (0x08U)
 The JEDEC JESD216 Revision is D.
 
#define CY_SMIF_SFDP_PARAM_TABLE_PTR   (0x0CU)
 Specifies the start of the JEDEC Basic Flash Parameter Table in the SFDP structure.
 
#define CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE   (0x00U)
 Code for the SFDP Address Bytes Number 3.
 
#define CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE   (0x01U)
 Code for the SFDP Address Bytes Number 3 or 4.
 
#define CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE   (0x02U)
 Code for the SFDP Address Bytes Number 4.
 
#define CY_SMIF_THREE_BYTES_ADDR   (0x03U)
 The address Bytes Number is 3.
 
#define CY_SMIF_FOUR_BYTES_ADDR   (0x04U)
 The address Bytes Number is 4.
 
#define CY_SMIF_READ_MODE_BYTE   (0x5AU)
 The mode byte for the SMIF read.
 
#define CY_SMIF_WRITE_STATUS_REG1_CMD   (0x01U)
 The write status register 1 command.
 
#define CY_SMIF_SINGLE_PROGRAM_CMD   (0x02U)
 The command for a single SMIF program.
 
#define CY_SMIF_SINGLE_READ_CMD   (0x03U)
 The command for a single SMIF read.
 
#define CY_SMIF_WRITE_DISABLE_CMD   (0x04U)
 The Write Disable command.
 
#define CY_SMIF_READ_STATUS_REG1_CMD   (0x05U)
 The read status register 1 command.
 
#define CY_SMIF_WRITE_ENABLE_CMD   (0x06U)
 The Write Enable command.
 
#define CY_SMIF_READ_STATUS_REG2_T1_CMD   (0x35U)
 The read status register 2 type 1 command.
 
#define CY_SMIF_WRITE_STATUS_REG2_T1_CMD   (0x3EU)
 The write status register 2 type 1 command.
 
#define CY_SMIF_WRITE_STATUS_REG2_T2_CMD   (0x31U)
 The write status register 2 type 2 command.
 
#define CY_SMIF_READ_STATUS_REG2_T2_CMD   (0x3FU)
 The read status register 2 type 2 command.
 
#define CY_SMIF_CHIP_ERASE_CMD   (0x60U)
 The Chip Erase command.
 
#define CY_SMIF_POWER_DOWN_CMD   (0xB9U)
 The Power-down command.
 
#define CY_SMIF_RELEASE_POWER_DOWN_CMD   (0xABU)
 The Release Power-down command.
 
#define CY_SMIF_QE_BIT_STATUS_REG2_T1   (0x02U)
 The QE bit is in status register 2 type 1. More...
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_1S   (0x0CU)
 The command for a 1S-1S-1S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_2S   (0x3CU)
 The command for a 1S-1S-2S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_2S_2S   (0xBCU)
 The command for a 1S-2S-2S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_4S   (0x6CU)
 The command for a 1S-1S-4S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4S_4S   (0xECU)
 The command for a 1S-4S-4S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_8S   (0x7CU)
 The command for a 1S-1S-8S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_8S_8S   (0xCCU)
 The command for a 1S-8S-8S SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4D_4D   (0xEEU)
 The command for a 1S-4D-4D SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_8D_8D   (0xFDU)
 The command for a 1S-8D-8D SMIF fast read with 4-byte addressing.
 
#define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_1S   (0x12U)
 The command for a 1S-1S-1S SMIF page program with 4-byte addressing.
 
#define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_4S   (0x34U)
 The command for a 1S-1S-4S SMIF page program with 4-byte addressing.
 
#define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_4S_4S   (0x3EU)
 The command for a 1S-4S-4S SMIF page program with 4-byte addressing.
 
#define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_8S   (0x84U)
 The command for a 1S-1S-8S SMIF page program with 4-byte addressing.
 
#define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_8S_8S   (0x8EU)
 The command for a 1S-8S-8S SMIF page program with 4-byte addressing.
 
#define CY_SMIF_BRWR_EXTADD_MASK   (0x80U)
 The Extended Address Enable (EXTADD) mask.
 
#define CY_SMIF_SFDP_ERASE_TIME_1MS   (1U)
 Units of Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_ERASE_TIME_16MS   (16U)
 Units of Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_ERASE_TIME_128MS   (128U)
 Units of Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_ERASE_TIME_1S   (1000U)
 Units of Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS   (16U)
 Units of Chip Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS   (256U)
 Units of Chip Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_4S   (4000U)
 Units of Chip Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_64S   (64000U)
 Units of Chip Erase Typical Time in ms.
 
#define CY_SMIF_SFDP_PROG_TIME_8US   (8U)
 Units of Page Program Typical Time in us.
 
#define CY_SMIF_SFDP_PROG_TIME_64US   (64U)
 Units of Page Program Typical Time in us.
 
#define CY_SMIF_SFDP_PROG_TIME_DEFAULT   (100000U)
 Default Page Program Time in us - 100 ms.
 
#define CY_SMIF_SFDP_PAGE_SIZE_DEFAULT   (256U)
 Default Page size used for SFDP 1.0 devices.
 
#define CY_SMIF_SFDP_UNIT_0   (0U)
 Units of Basic Flash Parameter Table Time Parameters.
 
#define CY_SMIF_SFDP_UNIT_1   (1U)
 Units of Basic Flash Parameter Table Time Parameters.
 
#define CY_SMIF_SFDP_UNIT_2   (2U)
 Units of Basic Flash Parameter Table Time Parameters.
 
#define CY_SMIF_SFDP_UNIT_3   (3U)
 Units of Basic Flash Parameter Table Time Parameters.
 
#define CY_SMIF_STATUS_REG_BUSY_MASK   (0x01U)
 The busy mask for the status registers.
 
#define CY_SMIF_NO_COMMAND_OR_MODE   (0xFFFFFFFFUL)
 No command or mode present.
 
#define CY_SMIF_SFDP_QE_BIT_1_OF_SR_2   (0x02UL)
 The QE is bit 1 of the status register 2.
 
#define CY_SMIF_SFDP_QE_BIT_6_OF_SR_1   (0x40UL)
 The QE is bit 6 of the status register 1.
 
#define CY_SMIF_SFDP_QE_BIT_7_OF_SR_2   (0x80UL)
 The QE is bit 7 of the status register 2.
 
#define CY_SMIF_SFDP_BFPT_BYTE_02   (0x02U)
 The byte 0x02 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_04   (0x04U)
 The byte 0x04 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_05   (0x05U)
 The byte 0x05 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_06   (0x06U)
 The byte 0x06 of the JEDEC Basic Flash Parameter Table: number of Parameter Headers (zero based, 05h = 6 parameters)
 
#define CY_SMIF_SFDP_BFPT_BYTE_08   (0x08U)
 The byte 0x08 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_09   (0x09U)
 The byte 0x09 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0A   (0x0AU)
 The byte 0x0A of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0B   (0x0BU)
 The byte 0x0B of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0C   (0x0CU)
 The byte 0x0C of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0D   (0x0DU)
 The byte 0x0D of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0E   (0x0EU)
 The byte 0x0E of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_0F   (0x0FU)
 The byte 0x0F of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_1C   (0x1CU)
 The byte 0x1C of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_1D   (0x1DU)
 The byte 0x1D of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_23   (0x23U)
 The byte 0x23 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_28   (0x28U)
 The byte 0x28 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_3A   (0x3AU)
 The byte 0x3A of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_3C   (0x3CU)
 The byte 0x3C of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_3F   (0x3FU)
 The byte 0x3F of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_40   (0x40U)
 The byte 0x40 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_41   (0x41U)
 The byte 0x41 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_42   (0x42U)
 The byte 0x42 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_43   (0x43U)
 The byte 0x43 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_88   (0x58U)
 The byte 0x58 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_BYTE_89   (0x59U)
 The byte 0x59 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_SFDP_BFPT_ERASE_BYTE   (36U)
 The byte 36 of the JEDEC Basic Flash Parameter Table.
 
#define CY_SMIF_JEDEC_BFPT_10TH_DWORD   (9U)
 Offset to JEDEC Basic Flash Parameter Table: 10th DWORD

 
#define CY_SMIF_JEDEC_BFPT_11TH_DWORD   (10U)
 Offset to JEDEC Basic Flash Parameter Table: 11th DWORD

 
#define CY_SMIF_SFDP_SCCR_MAP_BYTE_3B   (0x3BU)
 DWORD-16 of SCCR Map SPI table.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_WRITE_CMD_Pos   (0U)
 SCCR Map DWORD-16 Octal mode enable write command position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_WRITE_CMD_Msk   (0xFFU)
 SCCR Map DWORD-16 Octal mode enable write command mask.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_READ_CMD_Pos   (8U)
 SCCR Map DWORD-16 Octal mode enable read command position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_READ_CMD_Msk   (0xFF00U)
 SCCR Map DWORD-16 Octal mode enable read command mask.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_REG_ADDR_Pos   (16U)
 SCCR Map DWORD-16 Octal mode enable register address position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_REG_ADDR_Msk   (0xFF0000U)
 SCCR Map DWORD-16 Octal mode enable register address mask.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_Pos   (24U)
 SCCR Map DWORD-16 Octal mode enable bit position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_Msk   (0x7000000U)
 SCCR Map DWORD-16 Octal mode enable bit mask.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_USE_ADDRESS_Pos   (28U)
 SCCR Map DWORD-16 Octal mode enable uses address to set/clear position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_USE_ADDRESS_Msk   (0x10000000U)
 SCCR Map DWORD-16 Octal mode enable uses address to set/clear mask.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORT_Pos   (31U)
 SCCR Map DWORD-16 Octal mode enable bit support position.
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORT_Msk   (0x80000000U)
 SCCR Map DWORD-16 Octal mode enable bit support mask.
 
#define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET   (1UL)
 The offset for the detection command instruction in the Sector Map command descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_LEN_OFFSET   (2UL)
 The offset for the detection command address length in the Sector Map command descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET   (3UL)
 The offset for the read data mask in the Sector Map command descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET   (4UL)
 The offset for the detection command address in the Sector Map command descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET   (2UL)
 The offset for the regions count in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET   (2UL)
 The offset for the configuration ID in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK   (0xFU)
 The mask for the supported erase type code in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk   (0xC0UL)
 The mask for the configuration detection command address bytes in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos   (6UL)
 The position of the configuration detection command address bytes in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_DUMMY_CYCLES_Msk   (0xFUL)
 The mask for the configuration detection command read latency cycles in the Sector Map descriptor.
 
#define CY_SMIF_SFDP_SECTOR_MAP_DUMMY_CYCLES_Pos   (0UL)
 The position of the configuration detection command read latency cycles in the Sector Map descriptor.
 
#define FOUR_BYTE_ADDRESS_TABLE_BYTE_0   (0U)
 Byte 0x00 of the JEDEC 4-byte Address Instruction Table.
 
#define FOUR_BYTE_ADDRESS_TABLE_BYTE_1   (1U)
 Byte 0x01 of the JEDEC 4-byte Address Instruction Table.
 
#define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos   (6UL)
 The SFDP 1-1-4 fast read support (Bit 6)

 
#define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk   (0x40UL)
 The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01)
 
#define CY_SMIF_SFDP_FAST_READ_1_4_4_Pos   (5UL)
 The SFDP 1-4-4 fast read support (Bit 5)

 
#define CY_SMIF_SFDP_FAST_READ_1_4_4_Msk   (0x20UL)
 The SFDP 1-4-4 fast read support (Bitfield-Mask: 0x01)
 
#define CY_SMIF_SFDP_FAST_READ_1_2_2_Pos   (4UL)
 The SFDP 1-2-2 fast read support (Bit 4)

 
#define CY_SMIF_SFDP_FAST_READ_1_2_2_Msk   (0x10UL)
 The SFDP 1-2-2 fast read support (Bitfield-Mask: 0x01)
 
#define CY_SMIF_SFDP_DTR_SUPPORT_Pos   (3UL)
 The SFDP DTR support (Bit 3)

 
#define CY_SMIF_SFDP_DTR_SUPPORT_Msk   (0x08UL)
 The SFDP DTR support (Bitfield-Mask: 0x08)

 
#define CY_SMIF_SFDP_ADDRESS_BYTES_Pos   (1UL)
 The SFDP number of address bytes (Bit 1)

 
#define CY_SMIF_SFDP_ADDRESS_BYTES_Msk   (0x06UL)
 The SFDP number of address bytes (Bitfield-Mask: 0x03)
 
#define CY_SMIF_SFDP_FAST_READ_1_1_2_Pos   (0UL)
 The SFDP 1-1-2 fast read support (Bit 0)

 
#define CY_SMIF_SFDP_FAST_READ_1_1_2_Msk   (0x01UL)
 The SFDP 1-1-2 fast read support (Bitfield-Mask: 0x01)
 
#define CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk   (0x80000000UL)
 Flash memory density bit define if it >= 4 Gbit or <= 2Gbit.
 
#define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1-4-4 fast read dummy cycles (Bit 0)

 
#define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1-4-4 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1-4-4 fast read mode cycles (Bit 5)

 
#define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1-4-4 fast read mode cycles (Bitfield-Mask: 0x07)

 
#define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1-1-4 fast read dummy cycles (Bit 0)

 
#define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1-1-4 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1-1-4 fast read mode cycles (Bit 5)

 
#define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1-1-4 fast read mode cycles (Bitfield-Mask: 0x07)

 
#define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1_1_2 fast read dummy cycles (Bit 0)

 
#define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1_1_2 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1_1_2 fast read mode cycles (Bit 5)

 
#define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1_1_2 fast read mode cycles (Bitfield-Mask: 0x07)

 
#define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1_2_2 fast read dummy cycles (Bit 0)

 
#define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1_2_2 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1_2_2 fast read mode cycles (Bit 5)

 
#define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1_2_2 fast read mode cycles (Bitfield-Mask: 0x07)

 
#define CY_SMIF_SFDP_ERASE_T1_COUNT_Pos   (4UL)
 Erase Type 1 Erase, Typical time: count (Bits 8:4)
 
#define CY_SMIF_SFDP_ERASE_T1_COUNT_Msk   (0x1F0UL)
 Erase Type 1 Erase, Typical time: count (Bitfield-Mask )
 
#define CY_SMIF_SFDP_ERASE_T1_UNITS_Pos   (9UL)
 Erase Type 1 Erase, Typical time: units (Bits 10:9)
 
#define CY_SMIF_SFDP_ERASE_T1_UNITS_Msk   (0x600UL)
 Erase Type 1 Erase, Typical time: units (Bitfield-Mask )
 
#define CY_SMIF_SFDP_ERASE_MUL_COUNT_Pos   (0UL)
 Multiplier from typical erase time to maximum erase time (Bits 3:0)
 
#define CY_SMIF_SFDP_ERASE_MUL_COUNT_Msk   (0x0FUL)
 Multiplier from typical erase time to maximum erase time (Bitfield-Mask )
 
#define CY_SMIF_SFDP_PAGE_SIZE_Pos   (4UL)
 The SFDP page size (Bit 4)

 
#define CY_SMIF_SFDP_PAGE_SIZE_Msk   (0xF0UL)
 The SFDP page size (Bitfield-Mask: 0x0F)

 
#define CY_SMIF_SFDP_PAGE_PROG_COUNT_Pos   (8UL)
 The SFDP Chip Page Program Typical time: count (Bits 12:8)

 
#define CY_SMIF_SFDP_PAGE_PROG_COUNT_Msk   (0x1F00UL)
 The SFDP Chip Page Program Typical time: count (Bitfield-Mask)
 
#define CY_SMIF_SFDP_PAGE_PROG_UNITS_Pos   (13UL)
 The SFDP Chip Page Program Typical time: units (Bit 13)

 
#define CY_SMIF_SFDP_PAGE_PROG_UNITS_Msk   (0x2000UL)
 The SFDP Chip Page Program Typical time: units (Bitfield-Mask)
 
#define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Pos   (24UL)
 The SFDP Chip Erase Typical time: count (Bits 28:24)

 
#define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Msk   (0x1F000000UL)
 The SFDP Chip Erase Typical time: count (Bitfield-Mask)

 
#define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Pos   (29UL)
 The SFDP Chip Erase Typical time: units (Bits 29:30)

 
#define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Msk   (0x60000000UL)
 The SFDP Chip Erase Typical time: units (Bitfield-Mask)

 
#define CY_SMIF_SFDP_PROG_MUL_COUNT_Pos   (0UL)
 Multiplier from typical time to max time for Page or byte program (Bits 3:0)

 
#define CY_SMIF_SFDP_PROG_MUL_COUNT_Msk   (0x0FUL)
 Multiplier from typical time to max time for Page or byte program (Bitfield-Mask)

 
#define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos   (4UL)
 The SFDP quad enable requirements field (Bit 4)

 
#define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk   (0x70UL)
 The SFDP quad enable requirements field (Bitfield-Mask: 0x07)
 
#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7   (1U)
 Issue 0xB7 instruction.
 
#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7   (2U)
 Issue write enable instruction followed with 0xB7.
 
#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE   (0x40U)
 Memory always operates in 4-byte mode.
 
#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD   (0xB7U)
 The instruction required to enter 4-byte addressing mode.
 
#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_SUPPORTED_MASK   (0x7FU)
 Mask indicating 4-byte address mode entry supported.
 
#define CY_SMIF_SFDP_FAST_READ_1_1_8_Pos   (0UL)
 The SFDP 1-1-8 fast read support (Bitfield 24:31)

 
#define CY_SMIF_SFDP_FAST_READ_1_1_8_Msk   (0xFFUL)
 The SFDP 1-1-8 fast read support (Bitfield-Mask: 0xFF)
 
#define CY_SMIF_SFDP_1_1_8_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1-1-8 fast read mode cycles (Bitfield 21:23)

 
#define CY_SMIF_SFDP_1_1_8_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1-1-8 fast read mode cycles (Bitfield-Mask: 0xE)

 
#define CY_SMIF_SFDP_1_1_8_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1_1_8 fast read dummy cycles (Bit 16:19)

 
#define CY_SMIF_SFDP_1_1_8_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1_1_8 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_FAST_READ_1_8_8_Pos   (0UL)
 The SFDP 1-8-8 fast read support (Bitfield 8:15)

 
#define CY_SMIF_SFDP_FAST_READ_1_8_8_Msk   (0xFFUL)
 The SFDP 1-8-8 fast read support (Bitfield-Mask: 0xFF)
 
#define CY_SMIF_SFDP_1_8_8_MODE_CYCLES_Pos   (5UL)
 The SFDP number of 1-8-8 fast read mode cycles (Bitfield 5:7)

 
#define CY_SMIF_SFDP_1_8_8_MODE_CYCLES_Msk   (0xE0UL)
 The SFDP number of 1-8-8 fast read mode cycles (Bitfield-Mask: 0xE)

 
#define CY_SMIF_SFDP_1_8_8_DUMMY_CYCLES_Pos   (0UL)
 The SFDP number of 1_8_8 fast read dummy cycles (Bit 0:4)

 
#define CY_SMIF_SFDP_1_8_8_DUMMY_CYCLES_Msk   (0x1FUL)
 The SFDP number of 1_8_8 fast read dummy cycles (Bitfield-Mask: 0x1F)
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORTED_Pos   (20UL)
 Octal Enable bit present in the flash or not (Bitfield 20:22)
 
#define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORTED_Msk   (0x700000)
 Octal Enable bit present Mask (Bitfield-Mask 0x7)
 
#define CY_SMIF_SFDP_FAST_READ_DTR_CMD_1_4_4_Pos   (0UL)
 The SFDP 1-4-4 fast read support command (Bit 8:15)

 
#define CY_SMIF_SFDP_FAST_READ_DTR_CMD_1_4_4_Msk   (0xFFUL)
 The SFDP 1-4-4 fast read support command Mask

 
#define CY_SMIF_SFDP_FAST_READ_DTR_MODE_1_4_4_Pos   (5UL)
 The SFDP 1-4-4 fast read support mode (Bit 5:7)

 
#define CY_SMIF_SFDP_FAST_READ_DTR_MODE_1_4_4_Msk   (0xE0UL)
 The SFDP 1-4-4 fast read support mode Mask

 
#define CY_SMIF_SFDP_FAST_READ_DTR_DUMMY_CYCLES_1_4_4_Pos   (0UL)
 The SFDP 1-4-4 fast read support DTR Dummy cycles (Bit 0:4)

 
#define CY_SMIF_SFDP_FAST_READ_DTR_DUMMY_CYCLES_1_4_4_Msk   (0x1FUL)
 The SFDP 1-4-4 fast read support DTR Dummy cycles Mask

 
#define XSPI_PROFILE_1_TABLE_BYTE_0   (0U)
 Byte 0x00 of the JEDEC xSPI Profile 1.0.
 
#define XSPI_PROFILE_1_TABLE_BYTE_1   (1U)
 Byte 0x01 of the JEDEC xSPI Profile 1.0.
 
#define XSPI_PROFILE_1_TABLE_BYTE_16   (0x10U)
 DWORD 5 => Byte 16 of the JEDEC xSPI Profile 1.0.
 
#define CY_SMIF_SFDP_OCTAL_DDR_READ_CMD_Pos   (0UL)
 Octal DDR 8D-8D-8D read command support position (Bitfield 8:15)
 
#define CY_SMIF_SFDP_OCTAL_DDR_READ_CMD_Msk   (0xFFUL)
 Octal DDR 8D-8D-8D read command support Mask Bitfield-Mask: 0xFF00)
 
#define CY_SMIF_SFDP_ODDR_166MHZ_DUMMY_CYCLES_Pos   (27UL)
 Octal DDR 8D-8D-8D dummy cycles for 166 Mhz (Bitfield 27:31)
 
#define CY_SMIF_SFDP_ODDR_166MHZ_DUMMY_CYCLES_Msk   (0xF8000000UL)
 Octal DDR 8D-8D-8D dummy cycles for 166 Mhz Mask.
 
#define CY_SMIF_SFDP_ODDR_200MHZ_DUMMY_CYCLES_Pos   (7UL)
 Octal DDR 8D-8D-8D dummy cycles for 200 Mhz (Bitfield 7:11)
 
#define CY_SMIF_SFDP_ODDR_200MHZ_DUMMY_CYCLES_Msk   (0xF80UL)
 Octal DDR 8D-8D-8D dummy cycles for 200 Mhz Mask.
 
#define CMD_SEQ_OCTAL_DDR_CMD1_LEN_BYTE_OFFSET   (3U)
 Octal DDR enable command 1 sequence length byte offset.
 
#define CMD_SEQ_OCTAL_DDR_CMD2_LEN_BYTE_OFFSET   (11U)
 Octal DDR enable command 1 sequence length byte offset.
 
#define CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN   (8U)
 Octal DDR enable command sequence maximum length.
 
#define CY_SMIF_NOR_CFI_QUERY_CMD   (0x98)
 Following Hyperbus commands are to be used in a sequence as specified in the Hyper Flash/RAM data sheet. More...
 
#define CY_SMIF_NOR_CHIP_ERASE_CMD   (0x10)
 HyperBus NOR Chip Erase Command.
 
#define CY_SMIF_NOR_ERASE_SETUP_CMD   (0x80)
 HyperBus NOR Erase Setup Command.
 
#define CY_SMIF_NOR_RESET_CMD   (0xF0)
 HyperBus NOR Reset Command.
 
#define CY_SMIF_NOR_SECSI_SECTOR_ENTRY_CMD   (0x88)
 HyperBus NOR SECSI Sector Entry Command.
 
#define CY_SMIF_NOR_SECTOR_ERASE_CMD   (0x30)
 HyperBus NOR Sector Erase Command.
 
#define CY_SMIF_NOR_WRITE_BUFFER_LOAD_CMD   (0x25)
 HyperBus NOR Write Buffer load Command.
 
#define CY_SMIF_NOR_WRITE_BUFFER_PGM_CONFIRM_CMD   (0x29)
 HyperBus NOR Write Buffer Program Confirm Command.
 
#define CY_SMIF_NOR_SET_CONFIG_CMD   (0xD0)
 HyperBus NOR Set Config Command.
 
#define CY_SMIF_NOR_BIT_FIELD_CMD   (0xBF)
 HyperBus NOR Bit Field Command.
 
#define CY_SMIF_NOR_ERASE_SUSPEND_CMD   (0xB0)
 HyperBus NOR Erase Suspend Command.
 
#define CY_SMIF_NOR_ERASE_RESUME_CMD   (0x30)
 HyperBus NOR Erase Resume Command.
 
#define CY_SMIF_NOR_PROGRAM_SUSPEND_CMD   (0x51)
 HyperBus NOR Program Suspend Command.
 
#define CY_SMIF_NOR_PROGRAM_RESUME_CMD   (0x50)
 HyperBus NOR Program Resume Command.
 
#define CY_SMIF_NOR_STATUS_REG_READ_CMD   (0x70)
 HyperBus NOR Status Register Read Command.
 
#define CY_SMIF_NOR_STATUS_REG_CLEAR_CMD   (0x71)
 HyperBus NOR Status Register Clear Command.
 
#define CY_SMIF_NOR_BLANK_CHECK_CMD   (0x33)
 HyperBus NOR Blank Check Command.
 
#define CY_SMIF_ENTER_SPI_MODE_CMD   (0xF5)
 HyperBus NOR Enter SPI Mode Command.
 
#define CY_SMIF_NOR_AUTOSELECT_CMD   (0x90)
 Command code definition. More...
 
#define CY_SMIF_NOR_PROGRAM_CMD   (0xA0)
 HyperBus NOR Program Command.
 
#define CY_SMIF_NOR_SECSI_SECTOR_EXIT_SETUP_CMD   (0x90)
 HyperBus NOR SECSI Sector Exit Setup Command.
 
#define CY_SMIF_NOR_SECSI_SECTOR_EXIT_CMD   (0x00)
 HyperBus NOR SECSI Sector Exit Command.
 
#define CY_SMIF_NOR_UNLOCK_BYPASS_ENTRY_CMD   (0x20)
 HyperBus NOR Unlock Bypass Entry Command.
 
#define CY_SMIF_NOR_UNLOCK_BYPASS_PROGRAM_CMD   (0xA0)
 HyperBus NOR Unlock Bypass Program Command.
 
#define CY_SMIF_NOR_UNLOCK_BYPASS_RESET_CMD1   (0x90)
 HyperBus NOR Unlock Bypass Reset Command One.
 
#define CY_SMIF_NOR_UNLOCK_BYPASS_RESET_CMD2   (0x00)
 HyperBus NOR Unlock Bypass Reset Command Two.
 
#define CY_SMIF_NOR_UNLOCK_DATA1   (0xAA)
 HyperBus NOR Unlock Data One.
 
#define CY_SMIF_NOR_UNLOCK_DATA2   (0x55)
 HyperBus NOR Unlock Data Two.
 
#define CY_SMIF_NOR_SUSPEND_CMD   (0xB0)
 HyperBus NOR Suspend Command.
 
#define CY_SMIF_NOR_RESUME_CMD   (0x30)
 HyperBus NOR Resume Command.
 
#define CY_SMIF_NOR_READ_CONFIG_CMD   (0xC6)
 HyperBus NOR Read Config Command.
 
#define CY_SMIF_NOR_WRITE_BUFFER_ABORT_RESET_CMD   (0xF0)
 HyperBus NOR Write Buffer Abort Reset Command.
 
#define CY_SMIF_DEV_RDY_MASK   (0x80)
 -------------------------— Hyperbus Devise status register information -----------------— More...
 
#define CY_SMIF_DEV_ERASE_SUSP_MASK   (0x40)
 Erase Suspend Bit.
 
#define CY_SMIF_DEV_ERASE_MASK   (0x20)
 Erase Status Bit.
 
#define CY_SMIF_DEV_PROGRAM_MASK   (0x10)
 Program Status Bit.
 
#define CY_SMIF_DEV_RFU_MASK   (0x08)
 Reserved.
 
#define CY_SMIF_DEV_PROGRAM_SUSP_MASK   (0x04)
 Program Suspend Bit.
 
#define CY_SMIF_DEV_SEC_LOCK_MASK   (0x02)
 Sector lock Bit.
 
#define CY_SMIF_DEV_BANK_MASK   (0x01)
 Operation in current bank.
 
#define CY_SMIF_DEV_CRCSSB_MASK   (0x0100)
 CRC Suspend Bit, 1: suspend, 0: no suspend.
 
#define CY_SMIF_DEV_ESTAT_MASK   (0x01)
 Sector Erase Status Bit (for Evaluate Erase Status) More...
 
#define CY_SMIF_HB_FLASH_UNLOCK_ADDR1   0x00000555
 HyperBus Unlock Address One.
 
#define CY_SMIF_HB_FLASH_UNLOCK_ADDR2   0x000002AA
 HyperBus Unlock Address Two.
 
#define CY_SMIF_HB_FLASH_CFI_UNLOCK_ADDR1   0x00000055
 HyperBus CFI Unlock Address One.
 
#define CY_SMIF_TAP_NOT_FOUND   0xFFU
 Delay tap matching to memory not found.
 
#define CY_SMIF_MEM_CALIBRATION_DATA_PATTERN_LENGTH   12U
 Pattern length used for memory read transaction calibration.
 

Typedefs

typedef uint32_t CY_SMIF_FLASHDATA
 HyperBus Flash Data Type.
 

Macro Definition Documentation

◆ CY_SMIF_SFDP_SIGNATURE_BYTE_00

#define CY_SMIF_SFDP_SIGNATURE_BYTE_00   (0x00U)

The SFDP Signature byte 0x00.

Should be "S"

◆ CY_SMIF_SFDP_SIGNATURE_BYTE_01

#define CY_SMIF_SFDP_SIGNATURE_BYTE_01   (0x01U)

The SFDP Signature byte 0x01.

Should be "F"

◆ CY_SMIF_SFDP_SIGNATURE_BYTE_02

#define CY_SMIF_SFDP_SIGNATURE_BYTE_02   (0x02U)

The SFDP Signature byte 0x02.

Should be "D"

◆ CY_SMIF_SFDP_SIGNATURE_BYTE_03

#define CY_SMIF_SFDP_SIGNATURE_BYTE_03   (0x03U)

The SFDP Signature byte 0x03.

Should be "P"

◆ CY_SMIF_SFDP_MINOR_REV

#define CY_SMIF_SFDP_MINOR_REV   (0x04U)

The SFDP Header byte 0x04.

Defines the JEDEC JESD216 Revision

◆ CY_SMIF_SFDP_MAJOR_REV

#define CY_SMIF_SFDP_MAJOR_REV   (0x05U)

The SFDP Header byte 0x05.

Defines the SFDP Major Revision

◆ CY_SMIF_QE_BIT_STATUS_REG2_T1

#define CY_SMIF_QE_BIT_STATUS_REG2_T1   (0x02U)

The QE bit is in status register 2 type 1.

It should be written as the second byte.

◆ CY_SMIF_NOR_CFI_QUERY_CMD

#define CY_SMIF_NOR_CFI_QUERY_CMD   (0x98)

Following Hyperbus commands are to be used in a sequence as specified in the Hyper Flash/RAM data sheet.

Please check the Command Summery section in the respective data sheet for the sequence to be followed. LLD Command Definition HyperBus NOR CFI Query Command

◆ CY_SMIF_NOR_AUTOSELECT_CMD

#define CY_SMIF_NOR_AUTOSELECT_CMD   (0x90)

Command code definition.

HyperBus NOR Auto Select Command

◆ CY_SMIF_DEV_RDY_MASK

#define CY_SMIF_DEV_RDY_MASK   (0x80)

-------------------------— Hyperbus Devise status register information -----------------—

Device Ready Bit

◆ CY_SMIF_DEV_ESTAT_MASK

#define CY_SMIF_DEV_ESTAT_MASK   (0x01)

Sector Erase Status Bit (for Evaluate Erase Status)

0=previous erase did not complete successfully 1=previous erase completed successfully