Enumerated Types

General Description

Data Structures
struct	cy_stc_smif_bridge_pri_t
	Specifies the port priority on bridge interface. More...
struct	cy_stc_smif_bridge_remap_t
	Specifies the remap region information. More...
struct	cy_stc_smif_bridge_interleave_remap_t
	Specifies the interleaved memory region. More...

Macros
#define	CY_SMIF_CLKOUT_NON_ZERO_MDL_TAP_MIN_SDR   (CY_SMIF_MDL_3_TAP_DELAY) /* In SDR mode, when CLKOUT is not divide by two, this is the minimum acceptable MDL tap */
#define	CY_SMIF_CLKOUT_NON_ZERO_MDL_TAP_MAX_SDR   (CY_SMIF_MDL_13_TAP_DELAY) /* In SDR mode, when CLKOUT is not divide by two, this is the maximum acceptable MDL tap */
#define	CY_SMIF_CLKOUT_NON_ZERO_MDL_TAP_MIN_DDR   (CY_SMIF_MDL_3_TAP_DELAY) /* In DDR mode, when CLKOUT is not divide by two, this is the minimum acceptable MDL tap */
#define	CY_SMIF_CLKOUT_NON_ZERO_MDL_TAP_MAX_DDR   (CY_SMIF_MDL_14_TAP_DELAY) /* In DDR mode, when CLKOUT is not divide by two, this is the maximum acceptable MDL tap */

Enumerations
enum	cy_en_smif_txfr_width_t {   CY_SMIF_WIDTH_SINGLE = 0U ,   CY_SMIF_WIDTH_DUAL = 1U ,   CY_SMIF_WIDTH_QUAD = 2U ,   CY_SMIF_WIDTH_OCTAL = 3U ,   CY_SMIF_WIDTH_NA = 0xFFU }
	The Transfer width options for the command, data, the address and the mode. More...
enum	cy_en_smif_error_event_t {   CY_SMIF_BUS_ERROR = 0UL ,   CY_SMIF_WAIT_STATES = 1UL }
	The SMIF error-event selection. More...
enum	cy_en_smif_delay_line_t {   CY_SMIF_1_NEW_SEL_PER_TAP = 0 ,   CY_SMIF_1_SEL_PER_TAP = 1 ,   CY_SMIF_2_SEL_PER_TAP = 2 ,   CY_SMIF_4_SEL_PER_TAP = 3 ,   CY_SMIF_NO_DELAY_SEL = 0xFF }
	Specifies the delay line used for RX data capturing with More...
enum	cy_en_smif_data_select_t {   CY_SMIF_DATA_SEL0 = 0 ,   CY_SMIF_DATA_SEL1 = 1 ,   CY_SMIF_DATA_SEL2 = 2 ,   CY_SMIF_DATA_SEL3 = 3 }
	The data line-selection options for a slave device. More...
enum	cy_en_smif_mode_t {   CY_SMIF_NORMAL ,   CY_SMIF_MEMORY }
	The SMIF modes to work with an external memory. More...
enum	cy_en_smif_dll_divider_t {   CY_SMIF_DLL_DIVIDE_BY_2 = 0 ,   CY_SMIF_DLL_DIVIDE_BY_4 = 1 ,   CY_SMIF_DLL_DIVIDE_BY_8 = 2 ,   CY_SMIF_DLL_DIVIDE_BY_16 = 3 }
enum	cy_en_smif_tx_sdr_extra_t {   CY_SMIF_TX_ONE_PERIOD_AHEAD = 0 ,   CY_SMIF_TX_TWO_PERIOD_AHEAD = 1 }
enum	cy_en_cy_smif_mdl_tap_sel_t {   CY_SMIF_MDL_1_TAP_DELAY = 0 ,   CY_SMIF_MDL_2_TAP_DELAY = 1 ,   CY_SMIF_MDL_3_TAP_DELAY = 2 ,   CY_SMIF_MDL_4_TAP_DELAY = 3 ,   CY_SMIF_MDL_5_TAP_DELAY = 4 ,   CY_SMIF_MDL_6_TAP_DELAY = 5 ,   CY_SMIF_MDL_7_TAP_DELAY = 6 ,   CY_SMIF_MDL_8_TAP_DELAY = 7 ,   CY_SMIF_MDL_9_TAP_DELAY = 8 ,   CY_SMIF_MDL_10_TAP_DELAY = 9 ,   CY_SMIF_MDL_11_TAP_DELAY = 10 ,   CY_SMIF_MDL_12_TAP_DELAY = 11 ,   CY_SMIF_MDL_13_TAP_DELAY = 12 ,   CY_SMIF_MDL_14_TAP_DELAY = 13 ,   CY_SMIF_MDL_15_TAP_DELAY = 14 ,   CY_SMIF_MDL_16_TAP_DELAY = 15 ,   CY_SMIF_MDL_TAP_NUMBER = 16 }
enum	cy_en_cy_smif_sdl_tap_sel_t {   CY_SMIF_SDL_1_TAP_DELAY = 0 ,   CY_SMIF_SDL_2_TAP_DELAY = 1 ,   CY_SMIF_SDL_3_TAP_DELAY = 2 ,   CY_SMIF_SDL_4_TAP_DELAY = 3 ,   CY_SMIF_SDL_5_TAP_DELAY = 4 ,   CY_SMIF_SDL_6_TAP_DELAY = 5 ,   CY_SMIF_SDL_7_TAP_DELAY = 6 ,   CY_SMIF_SDL_8_TAP_DELAY = 7 ,   CY_SMIF_SDL_9_TAP_DELAY = 8 ,   CY_SMIF_SDL_10_TAP_DELAY = 9 ,   CY_SMIF_SDL_11_TAP_DELAY = 10 ,   CY_SMIF_SDL_12_TAP_DELAY = 11 ,   CY_SMIF_SDL_13_TAP_DELAY = 12 ,   CY_SMIF_SDL_14_TAP_DELAY = 13 ,   CY_SMIF_SDL_15_TAP_DELAY = 14 ,   CY_SMIF_SDL_16_TAP_DELAY = 15 ,   CY_SMIF_SDL_TAP_NUMBER = 16 }
enum	cy_en_cy_smif_ddl_tap_sel_t {   CY_SMIF_DDL_1_TAP_DELAY = 0 ,   CY_SMIF_DDL_2_TAP_DELAY = 1 ,   CY_SMIF_DDL_3_TAP_DELAY = 2 ,   CY_SMIF_DDL_4_TAP_DELAY = 3 ,   CY_SMIF_DDL_5_TAP_DELAY = 4 ,   CY_SMIF_DDL_6_TAP_DELAY = 5 ,   CY_SMIF_DDL_7_TAP_DELAY = 6 ,   CY_SMIF_DDL_8_TAP_DELAY = 7 ,   CY_SMIF_DDL_9_TAP_DELAY = 8 ,   CY_SMIF_DDL_10_TAP_DELAY = 9 ,   CY_SMIF_DDL_11_TAP_DELAY = 10 ,   CY_SMIF_DDL_12_TAP_DELAY = 11 ,   CY_SMIF_DDL_13_TAP_DELAY = 12 ,   CY_SMIF_DDL_14_TAP_DELAY = 13 ,   CY_SMIF_DDL_15_TAP_DELAY = 14 ,   CY_SMIF_DDL_16_TAP_DELAY = 15 ,   CY_SMIF_DDL_TAP_NUMBER = 16 }
enum	cy_en_smif_delay_tap_t {   CY_SMIF_DELAY_TAP_DISABLE = 0 ,   CY_SMIF_DELAY_TAP_ENABLE = 1 }
enum	cy_en_smif_txfr_status_t {   CY_SMIF_STARTED ,   CY_SMIF_SEND_COMPLETE ,   CY_SMIF_SEND_BUSY ,   CY_SMIF_RX_COMPLETE ,   CY_SMIF_RX_BUSY ,   CY_SMIF_XIP_ERROR ,   CY_SMIF_CMD_ERROR ,   CY_SMIF_TX_ERROR ,   CY_SMIF_RX_ERROR }
	The SMIF transfer status return values. More...
enum	cy_en_smif_status_t {   CY_SMIF_SUCCESS = 0x00U ,   CY_SMIF_CMD_FIFO_FULL = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x01U ,   CY_SMIF_EXCEED_TIMEOUT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x02U ,   CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U ,   CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U ,   CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U ,   CY_SMIF_NOT_HYBRID_MEM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x06U ,   CY_SMIF_SFDP_CORRUPTED_TABLE = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x07U ,   CY_SMIF_SFDP_SS0_FAILED ,   CY_SMIF_SFDP_SS1_FAILED ,   CY_SMIF_SFDP_SS2_FAILED ,   CY_SMIF_SFDP_SS3_FAILED ,   CY_SMIF_CMD_NOT_FOUND = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x80U ,   CY_SMIF_SFDP_BUFFER_INSUFFICIENT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x81U ,   CY_SMIF_NO_OE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x82U ,   CY_SMIF_BUSY = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x83U ,   CY_SMIF_GENERAL_ERROR = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x84U ,   CY_SMIF_SECURITY_POLICY_VIOLATION = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x90U }
	The SMIF API return values. More...
enum	cy_en_smif_slave_select_t {   CY_SMIF_SLAVE_SELECT_0 = 1U ,   CY_SMIF_SLAVE_SELECT_1 = 2U ,   CY_SMIF_SLAVE_SELECT_2 = 4U ,   CY_SMIF_SLAVE_SELECT_3 = 8U }
	The SMIF slave select definitions for the driver API. More...
enum	cy_en_smif_capture_mode_t {   CY_SMIF_SEL_NORMAL_SPI = 0U ,   CY_SMIF_SEL_NORMAL_SPI_WITH_DLP = 1U ,   CY_SMIF_SEL_XSPI_HYPERBUS_WITH_DQS = 2U }
	Specifies receive capture mode. More...
enum	cy_en_smif_clk_select_t {   CY_SMIF_SEL_OUTPUT_CLK = 0U ,   CY_SMIF_SEL_INVERTED_OUTPUT_CLK = 1U ,   CY_SMIF_SEL_FEEDBACK_CLK = 2U ,   CY_SMIF_SEL_INVERTED_FEEDBACK_CLK = 3U ,   CY_SMIF_SEL_INTERNAL_CLK = 4U ,   CY_SMIF_SEL_INVERTED_INTERNAL_CLK = 5U ,   CY_SMIF_SEL_INVERTED_SPHB_RWDS_CLK = 6U ,   CY_SMIF_SEL_SPHB_RWDS_CLK = 7U }
	Specifies the clock source for the receiver clock. More...
enum	cy_en_smif_cache_t {   CY_SMIF_CACHE_SLOW = 1U ,   CY_SMIF_CACHE_FAST = 2U ,   CY_SMIF_CACHE_BOTH = 3U }
	Specifies enabled type of SMIF cache. More...
enum	cy_en_smif_qer_t {   CY_SMIF_SFDP_QER_0 = 0 ,   CY_SMIF_SFDP_QER_1 = 1 ,   CY_SMIF_SFDP_QER_2 = 2 ,   CY_SMIF_SFDP_QER_3 = 3 ,   CY_SMIF_SFDP_QER_4 = 4 ,   CY_SMIF_SFDP_QER_5 = 5 ,   CY_SMIF_SFDP_QER_6 = 6 }
	Specifies the quad enable requirement case. More...
enum	cy_en_smif_interface_freq_t {   CY_SMIF_100MHZ_OPERATION = 0 ,   CY_SMIF_133MHZ_OPERATION = 1 ,   CY_SMIF_166MHZ_OPERATION = 2 ,   CY_SMIF_200MHZ_OPERATION = 3 }
	Specifies the memory interface frequency range of operation. More...
enum	cy_en_smif_data_rate_t {   CY_SMIF_SDR = 0 ,   CY_SMIF_DDR = 1 }
	Specifies the data rate. More...
enum	cy_en_smif_field_presence_t {   CY_SMIF_NOT_PRESENT = 0 ,   CY_SMIF_PRESENT_1BYTE = 1 ,   CY_SMIF_PRESENT_2BYTE = 2 }
	Specifies the presence of the field.
enum	cy_en_smif_merge_timeout_t {   CY_SMIF_MERGE_TIMEOUT_1_CYCLE = 0 ,   CY_SMIF_MERGE_TIMEOUT_16_CYCLES = 1 ,   CY_SMIF_MERGE_TIMEOUT_256_CYCLES = 2 ,   CY_SMIF_MERGE_TIMEOUT_4096_CYCLES = 3 ,   CY_SMIF_MERGE_TIMEOUT_65536_CYCLES = 4 }
	Specifies the merge transaction timeout in terms of clock cycles.
enum	cy_en_smif_bridge_xip_space_pri_t {   CY_SMIF_EN_BRIDGE_PRIO_SMIF0_XIP_SPACE = 0 ,   CY_SMIF_EN_BRIDGE_PRIO_SMIF1_XIP_SPACE = 1 }
	Specifies the PORT priority for XIP space.
enum	cy_en_smif_bridge_xip_space_t {   CY_SMIF_EN_BRIDGE_SMIF0_XIP_SPACE = 0 ,   CY_SMIF_EN_BRIDGE_SMIF1_XIP_SPACE = 1 }
	Specifies the XIP space.
enum	cy_en_smif_bridge_remap_type_t {   CY_SMIF_EN_BRIDGE_REMAP_TYPE_INACTIVE = 0 ,   CY_SMIF_EN_BRIDGE_REMAP_TYPE_TO_SMIF0 = 1 ,   CY_SMIF_EN_BRIDGE_REMAP_TYPE_TO_SMIF1 = 2 ,   CY_SMIF_EN_BRIDGE_REMAP_TYPE_INTERLEAVE = 3 }
	Specifies the remap type.
enum	cy_en_smif_bridge_interleave_step_t {   CY_SMIF_EN_BRIDGE_INTERLEAVE_8BYTE = 0 ,   CY_SMIF_EN_BRIDGE_INTERLEAVE_16BYTE = 1 ,   CY_SMIF_EN_BRIDGE_INTERLEAVE_32BYTE = 2 ,   CY_SMIF_EN_BRIDGE_INTERLEAVE_64BYTE = 3 ,   CY_SMIF_EN_BRIDGE_INTERLEAVE_128BYTE = 4 }
	Specifies the interleave size.
enum	cy_en_smif_bridge_remap_region_size_t {   CY_SMIF_EN_BRIDGE_REMAP_SIZE_1MB = 0x1FF00000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_2MB = 0x1FE00000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_4MB = 0x1FC00000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_8MB = 0x1F800000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_16MB = 0x1F000000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_32MB = 0x1E000000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_64MB = 0x1C000000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_128MB = 0x18000000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_256MB = 0x10000000U ,   CY_SMIF_EN_BRIDGE_REMAP_SIZE_512MB = 0x00000000U }
	Specifies the remap size.
enum	cy_en_smif_mem_data_line_t {   CY_SMIF_DATA_BIT0_TAP_SEL = 0U ,   CY_SMIF_DATA_BIT1_TAP_SEL = 1U ,   CY_SMIF_DATA_BIT2_TAP_SEL = 2U ,   CY_SMIF_DATA_BIT3_TAP_SEL = 3U ,   CY_SMIF_DATA_BIT4_TAP_SEL = 4U ,   CY_SMIF_DATA_BIT5_TAP_SEL = 5U ,   CY_SMIF_DATA_BIT6_TAP_SEL = 6U ,   CY_SMIF_DATA_BIT7_TAP_SEL = 7U }
	Specifies the data line index. More...
enum	cy_en_sdr_cap_style_t {   CY_SMIF_RX_CAP_STYLE_SDR_POS = 0 ,   CY_SMIF_RX_CAP_STYLE_SDR_NEG_NORM = 1 ,   CY_SMIF_RX_CAP_STYLE_SDR_NEG_PIPED = 2 }
	Specifies the sdr cap style.
enum	cy_en_smif_cache_attribute_t {   CY_SMIF_NON_CACHEABLE_NON_BUFFERABLE = 0x00 ,   CY_SMIF_NON_CACHEABLE_BUFFERABLE = 0x01 ,   CY_SMIF_CACHEABLE_WT_WA = 0x0E ,   CY_SMIF_CACHEABLE_WT_RA = 0x16 ,   CY_SMIF_CACHEABLE_WT_RWA = 0x1E ,   CY_SMIF_CACHEABLE_WB_WA = 0x0F ,   CY_SMIF_CACHEABLE_WB_RA = 0x17 ,   CY_SMIF_CACHEABLE_WB_RWA = 0x1F }
	Specifies CACHE region attribute. More...

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Data Structure Documentation

cy_stc_smif_bridge_pri_t

struct cy_stc_smif_bridge_pri_t

Data Fields
cy_en_smif_bridge_xip_space_pri_t	pri_ahb_smif0	This specifies the priority for AHB access over SMIF0.
cy_en_smif_bridge_xip_space_pri_t	pri_ahb_smif1	This specifies the priority for AHB access over SMIF1.
cy_en_smif_bridge_xip_space_pri_t	pri_axi_smif0	This specifies the priority for AXI access over SMIF0.
cy_en_smif_bridge_xip_space_pri_t	pri_axi_smif1	This specifies the priority for AXI access over SMIF1.

cy_stc_smif_bridge_remap_t

struct cy_stc_smif_bridge_remap_t

Data Fields
uint32_t	regionIdx	This specifies the region index (0..8)
cy_en_smif_bridge_remap_region_size_t	regionSize	This specifies the region size.
uint32_t	xipAddr	This specifies XIP address to be remapped.
uint32_t	phyAddr	This specifies target remapped address.

cy_stc_smif_bridge_interleave_remap_t

struct cy_stc_smif_bridge_interleave_remap_t

Data Fields
uint32_t	regionIdx	This specifies the region index (0..8)
cy_en_smif_bridge_remap_region_size_t	regionSize	This specifies the region size.
uint32_t	xipAddr	This specifies XIP address to be remapped.
uint32_t	phyAddr0	This specifies remapped address on PORT0.
uint32_t	phyAddr1	This specifies remapped address on PORT1.

Enumeration Type Documentation

cy_en_smif_txfr_width_t

enum cy_en_smif_txfr_width_t

The Transfer width options for the command, data, the address and the mode.

Enumerator
CY_SMIF_WIDTH_SINGLE	Single SPI mode.
CY_SMIF_WIDTH_DUAL	Dual SPI mode.
CY_SMIF_WIDTH_QUAD	Quad SPI mode.
CY_SMIF_WIDTH_OCTAL	Octal SPI mode.
CY_SMIF_WIDTH_NA	The specific width parameter is not applicable for this memory command.

cy_en_smif_error_event_t

enum cy_en_smif_error_event_t

The SMIF error-event selection.

Enumerator
CY_SMIF_BUS_ERROR	Generates a bus error.
CY_SMIF_WAIT_STATES	Stalls the bus with the wait states. This option will increase the interrupt latency.

cy_en_smif_delay_line_t

enum cy_en_smif_delay_line_t

Specifies the delay line used for RX data capturing with

Enumerator
CY_SMIF_1_NEW_SEL_PER_TAP	1 of these new delay cells per tap providing: granularity of max. ~0.22ns
CY_SMIF_1_SEL_PER_TAP	1 cell per tap providing: granularity of max. ~0.4ns
CY_SMIF_2_SEL_PER_TAP	2 cells per tap providing: granularity of max. ~0.8ns
CY_SMIF_4_SEL_PER_TAP	4 cells per tap providing: granularity of max. ~1.6ns
CY_SMIF_NO_DELAY_SEL	No delay line (disabled)

cy_en_smif_data_select_t

enum cy_en_smif_data_select_t

The data line-selection options for a slave device.

Enumerator
CY_SMIF_DATA_SEL0	smif.spi_data[0] = DATA0, smif.spi_data[1] = DATA1, ..., smif.spi_data[7] = DATA7. This value is allowed for the SPI, DSPI, QSPI, dual QSPI, and octal SPI modes.
CY_SMIF_DATA_SEL1	smif.spi_data[2] = DATA0, smif.spi_data[3] = DATA1. This value is only allowed for the SPI and DSPI modes.
CY_SMIF_DATA_SEL2	smif.spi_data[4] = DATA0, smif.spi_data[5] = DATA1, ..., smif.spi_data[7] = DATA3. This value is only allowed for the SPI, DSPI, QSPI and dual QSPI modes.
CY_SMIF_DATA_SEL3	smif.spi_data[6] = DATA0, smif.spi_data[7] = DATA1. This value is only allowed for the SPI and DSPI modes.

cy_en_smif_mode_t

enum cy_en_smif_mode_t

The SMIF modes to work with an external memory.

Enumerator
CY_SMIF_NORMAL	Command mode (MMIO mode).
CY_SMIF_MEMORY	XIP (eXecute In Place) mode.

cy_en_smif_dll_divider_t

enum cy_en_smif_dll_divider_t

Enumerator
CY_SMIF_DLL_DIVIDE_BY_2	Divides DLL Clock by 2.
CY_SMIF_DLL_DIVIDE_BY_4	Divides DLL Clock by 4.
CY_SMIF_DLL_DIVIDE_BY_8	Divides DLL Clock by 8.
CY_SMIF_DLL_DIVIDE_BY_16	Divides DLL Clock by 16.

cy_en_smif_tx_sdr_extra_t

enum cy_en_smif_tx_sdr_extra_t

Enumerator
CY_SMIF_TX_ONE_PERIOD_AHEAD	transmit data is launched nominally 1 PLL clock period ahead of the rising edge of the clock out to the memory
CY_SMIF_TX_TWO_PERIOD_AHEAD	transmit data is launched nominally 2 PLL clock periods ahead of the rising edge of the clock out to the memory

cy_en_cy_smif_mdl_tap_sel_t

enum cy_en_cy_smif_mdl_tap_sel_t

Enumerator
CY_SMIF_MDL_1_TAP_DELAY	1 tap delay
CY_SMIF_MDL_2_TAP_DELAY	2 tap delay
CY_SMIF_MDL_3_TAP_DELAY	3 tap delay
CY_SMIF_MDL_4_TAP_DELAY	4 tap delay
CY_SMIF_MDL_5_TAP_DELAY	5 tap delay
CY_SMIF_MDL_6_TAP_DELAY	6 tap delay
CY_SMIF_MDL_7_TAP_DELAY	7 tap delay
CY_SMIF_MDL_8_TAP_DELAY	8 tap delay
CY_SMIF_MDL_9_TAP_DELAY	9 tap delay
CY_SMIF_MDL_10_TAP_DELAY	10 tap delay
CY_SMIF_MDL_11_TAP_DELAY	11 tap delay
CY_SMIF_MDL_12_TAP_DELAY	12 tap delay
CY_SMIF_MDL_13_TAP_DELAY	13 tap delay
CY_SMIF_MDL_14_TAP_DELAY	14 tap delay
CY_SMIF_MDL_15_TAP_DELAY	15 tap delay
CY_SMIF_MDL_16_TAP_DELAY	16 tap delay
CY_SMIF_MDL_TAP_NUMBER	Tap Count.

cy_en_cy_smif_sdl_tap_sel_t

enum cy_en_cy_smif_sdl_tap_sel_t

Enumerator
CY_SMIF_SDL_1_TAP_DELAY	1 tap delay
CY_SMIF_SDL_2_TAP_DELAY	2 tap delay
CY_SMIF_SDL_3_TAP_DELAY	3 tap delay
CY_SMIF_SDL_4_TAP_DELAY	4 tap delay
CY_SMIF_SDL_5_TAP_DELAY	5 tap delay
CY_SMIF_SDL_6_TAP_DELAY	6 tap delay
CY_SMIF_SDL_7_TAP_DELAY	7 tap delay
CY_SMIF_SDL_8_TAP_DELAY	8 tap delay
CY_SMIF_SDL_9_TAP_DELAY	9 tap delay
CY_SMIF_SDL_10_TAP_DELAY	10 tap delay
CY_SMIF_SDL_11_TAP_DELAY	11 tap delay
CY_SMIF_SDL_12_TAP_DELAY	12 tap delay
CY_SMIF_SDL_13_TAP_DELAY	13 tap delay
CY_SMIF_SDL_14_TAP_DELAY	14 tap delay
CY_SMIF_SDL_15_TAP_DELAY	15 tap delay
CY_SMIF_SDL_16_TAP_DELAY	16 tap delay
CY_SMIF_SDL_TAP_NUMBER	Tap Count.

cy_en_cy_smif_ddl_tap_sel_t

enum cy_en_cy_smif_ddl_tap_sel_t

Enumerator
CY_SMIF_DDL_1_TAP_DELAY	1 tap delay
CY_SMIF_DDL_2_TAP_DELAY	2 tap delay
CY_SMIF_DDL_3_TAP_DELAY	3 tap delay
CY_SMIF_DDL_4_TAP_DELAY	4 tap delay
CY_SMIF_DDL_5_TAP_DELAY	5 tap delay
CY_SMIF_DDL_6_TAP_DELAY	6 tap delay
CY_SMIF_DDL_7_TAP_DELAY	7 tap delay
CY_SMIF_DDL_8_TAP_DELAY	8 tap delay
CY_SMIF_DDL_9_TAP_DELAY	9 tap delay
CY_SMIF_DDL_10_TAP_DELAY	10 tap delay
CY_SMIF_DDL_11_TAP_DELAY	11 tap delay
CY_SMIF_DDL_12_TAP_DELAY	12 tap delay
CY_SMIF_DDL_13_TAP_DELAY	13 tap delay
CY_SMIF_DDL_14_TAP_DELAY	14 tap delay
CY_SMIF_DDL_15_TAP_DELAY	15 tap delay
CY_SMIF_DDL_16_TAP_DELAY	16 tap delay
CY_SMIF_DDL_TAP_NUMBER	Tap Count.

cy_en_smif_delay_tap_t

enum cy_en_smif_delay_tap_t

Enumerator
CY_SMIF_DELAY_TAP_DISABLE	The SMIF Delay tap disable.
CY_SMIF_DELAY_TAP_ENABLE	The SMIF Delay tap enable.

cy_en_smif_txfr_status_t

enum cy_en_smif_txfr_status_t

The SMIF transfer status return values.

Enumerator
CY_SMIF_STARTED	The SMIF started.
CY_SMIF_SEND_COMPLETE	The data transmission is complete.
CY_SMIF_SEND_BUSY	The data transmission is in progress.
CY_SMIF_RX_COMPLETE	The data reception is completed.
CY_SMIF_RX_BUSY	The data reception is in progress.
CY_SMIF_XIP_ERROR	An XIP alignment error.
CY_SMIF_CMD_ERROR	A TX CMD FIFO overflow.
CY_SMIF_TX_ERROR	A TX DATA FIFO overflow.
CY_SMIF_RX_ERROR	An RX DATA FIFO underflow.

cy_en_smif_status_t

enum cy_en_smif_status_t

The SMIF API return values.

Enumerator
CY_SMIF_SUCCESS	Successful SMIF operation.
CY_SMIF_CMD_FIFO_FULL	The command is cancelled. The command FIFO is full.
CY_SMIF_EXCEED_TIMEOUT	The SMIF operation timeout exceeded.
CY_SMIF_NO_QE_BIT	The device does not have a QE bit. The device detects 1-1-4 and 1-4-4 Reads based on the instruction.
CY_SMIF_BAD_PARAM	The SMIF API received the wrong parameter.
CY_SMIF_NO_SFDP_SUPPORT	The external memory does not support SFDP (JESD216B).
CY_SMIF_NOT_HYBRID_MEM	The external memory is not hybrid.
CY_SMIF_SFDP_CORRUPTED_TABLE	The SFDP table is corrupted.
CY_SMIF_SFDP_SS0_FAILED	Failed to initialize the slave select 0 external memory by auto detection (SFDP).
CY_SMIF_SFDP_SS1_FAILED	Failed to initialize the slave select 1 external memory by auto detection (SFDP).
CY_SMIF_SFDP_SS2_FAILED	Failed to initialize the slave select 2 external memory by auto detection (SFDP).
CY_SMIF_SFDP_SS3_FAILED	Failed to initialize the slave select 3 external memory by auto detection (SFDP).
CY_SMIF_CMD_NOT_FOUND	The command API is not supported for this memory device.
CY_SMIF_SFDP_BUFFER_INSUFFICIENT	SFDP Buffer Insufficient.
CY_SMIF_NO_OE_BIT	The device does not have a OE bit. The device detects 1-1-8 and 1-8-8 Reads based on the instruction.
CY_SMIF_BUSY	SMIF is currently busy and cannot accept the request.
CY_SMIF_GENERAL_ERROR	Some general error.

cy_en_smif_slave_select_t

enum cy_en_smif_slave_select_t

The SMIF slave select definitions for the driver API.

Each slave select is represented by an enumeration that has the bit corresponding to the slave select number set.

Enumerator
CY_SMIF_SLAVE_SELECT_0	The SMIF slave select 0
CY_SMIF_SLAVE_SELECT_1	The SMIF slave select 1
CY_SMIF_SLAVE_SELECT_2	The SMIF slave select 2
CY_SMIF_SLAVE_SELECT_3	The SMIF slave select 3

cy_en_smif_capture_mode_t

enum cy_en_smif_capture_mode_t

Specifies receive capture mode.

Enumerator
CY_SMIF_SEL_NORMAL_SPI	Normal SPI without DLP.
CY_SMIF_SEL_NORMAL_SPI_WITH_DLP	Normal SPI with DLP (Data Learning Pattern).
CY_SMIF_SEL_XSPI_HYPERBUS_WITH_DQS	xSPI or HYPER BUS with Data strobe line.

cy_en_smif_clk_select_t

enum cy_en_smif_clk_select_t

Specifies the clock source for the receiver clock.

Enumerator
CY_SMIF_SEL_OUTPUT_CLK	The SMIF output clock.
CY_SMIF_SEL_INVERTED_OUTPUT_CLK	The SMIF inverted output clock.
CY_SMIF_SEL_FEEDBACK_CLK	The SMIF feedback clock.
CY_SMIF_SEL_INVERTED_FEEDBACK_CLK	The SMIF feedback inverted clock.
CY_SMIF_SEL_INTERNAL_CLK	The SMIF internal clock.
CY_SMIF_SEL_INVERTED_INTERNAL_CLK	The SMIF internal inverted clock.
CY_SMIF_SEL_INVERTED_SPHB_RWDS_CLK	The SMIF internal inverted clock.
CY_SMIF_SEL_SPHB_RWDS_CLK	The SMIF internal inverted clock.

cy_en_smif_cache_t

enum cy_en_smif_cache_t

Specifies enabled type of SMIF cache.

Enumerator
CY_SMIF_CACHE_SLOW	The SMIF slow cache (in the clk_slow domain) see TRM for details.
CY_SMIF_CACHE_FAST	The SMIF fast cache (in the clk_fast domain) see TRM for details.
CY_SMIF_CACHE_BOTH	The SMIF both caches.

cy_en_smif_qer_t

enum cy_en_smif_qer_t

Specifies the quad enable requirement case.

JEDEC Basic Flash Parameter Table: 15th DWORD

Enumerator
CY_SMIF_SFDP_QER_0	No QE Bit.
CY_SMIF_SFDP_QER_1	Bit 1 of Status Register 2 - Write uses 2 bytes using 01h.
CY_SMIF_SFDP_QER_2	Bit 6 of Status Register 1 - Write uses 1 byte.
CY_SMIF_SFDP_QER_3	Bit 7 of Status Register 2- Write uses 1 byte.
CY_SMIF_SFDP_QER_4	Bit 1 of Status Register 2 - Write uses 1 or 2 bytes.
CY_SMIF_SFDP_QER_5	Bit 1 of Status Register 2 - Write status uses 01h.
CY_SMIF_SFDP_QER_6	Bit 1 of Status Register 2 - Write uses 1 byte using 31h.

cy_en_smif_interface_freq_t

enum cy_en_smif_interface_freq_t

Specifies the memory interface frequency range of operation.

Enumerator
CY_SMIF_100MHZ_OPERATION	100 MHz default operation
CY_SMIF_133MHZ_OPERATION	133 MHz operation
CY_SMIF_166MHZ_OPERATION	166 MHz operation
CY_SMIF_200MHZ_OPERATION	200 MHz operation

cy_en_smif_data_rate_t

enum cy_en_smif_data_rate_t

Specifies the data rate.

Enumerator
CY_SMIF_SDR	The SMIF Single Data Rate (SDR)
CY_SMIF_DDR	The SMIF Double Data Rate (DDR)

cy_en_smif_mem_data_line_t

enum cy_en_smif_mem_data_line_t

Specifies the data line index.

Enumerator
CY_SMIF_DATA_BIT0_TAP_SEL	Data line zero.
CY_SMIF_DATA_BIT1_TAP_SEL	Data line one.
CY_SMIF_DATA_BIT2_TAP_SEL	Data line two.
CY_SMIF_DATA_BIT3_TAP_SEL	Data line three.
CY_SMIF_DATA_BIT4_TAP_SEL	Data line four.
CY_SMIF_DATA_BIT5_TAP_SEL	Data line five.
CY_SMIF_DATA_BIT6_TAP_SEL	Data line six.
CY_SMIF_DATA_BIT7_TAP_SEL	Data line seven.

cy_en_smif_cache_attribute_t

enum cy_en_smif_cache_attribute_t

Specifies CACHE region attribute.

Enumerator
CY_SMIF_NON_CACHEABLE_NON_BUFFERABLE	Non-Cacheable, Non-Bufferable (reset value)
CY_SMIF_NON_CACHEABLE_BUFFERABLE	Non-Cacheable, Bufferable
CY_SMIF_CACHEABLE_WT_WA	Cacheable, Write Through, Write Allocate.
CY_SMIF_CACHEABLE_WT_RA	Cacheable, Write Through, Read Allocate.
CY_SMIF_CACHEABLE_WT_RWA	Cacheable, Write Through, Read & Write Allocate.
CY_SMIF_CACHEABLE_WB_WA	Cacheable, Write Back, Write Allocate.
CY_SMIF_CACHEABLE_WB_RA	Cacheable, Write Back, Read Allocate.
CY_SMIF_CACHEABLE_WB_RWA	Cacheable, Write Back, Read & Write Allocate.