Data Structures

General Description

Data Structures
struct	cy_stc_ethif_wrapper_config_t
	Wrapper Configuration. More...
struct	cy_stc_ethif_queue_disablestatus_t
	Tx/Rx Queue status. More...
struct	cy_stc_ethif_buff_addr_t
	Virtual and physical addresses of DMA-addressable data buffer. More...
struct	cy_stc_ethif_bufstatus_t
	Buffer status. More...
struct	cy_stc_ethif_1588_timer_val_t
	1588 Timer value More...
struct	cy_stc_ethif_timer_increment_t
	writing/reading the 1588 timer increment registers More...
struct	cy_stc_ethif_tsu_config_t
	struct for writing/reading 1588 timer More...
struct	cy_stc_ethif_cb_t
	Ethernet MAC call back handlers. More...
struct	cy_stc_ethif_mac_config_t
	Ethernet MAC detailed configurations. More...
struct	cy_stc_ethif_intr_config_t
	Interrupt configuration for Ethernet MAC. More...
struct	cy_stc_ethif_mac_address_t
	Ethernet MAC Address. More...
struct	cy_stc_ethif_filter_config_t
	filter configuration for Ethernet MAC More...

Typedefs
typedef void(*	cy_ethif_tx_msg_cb_t) (ETH_Type *base, uint8_t u8QueueIndex)
	Frame transmission complete callback function. More...
typedef void(*	cy_ethif_tx_error_cb_t) (ETH_Type *base, uint8_t u8QueueIndex)
	Frame transmission Error callback function. More...
typedef void(*	cy_ethif_rx_frame_cb_t) (ETH_Type *base, uint8_t *u8RxBuffer, uint32_t u32Length)
	Frame received callback function. More...
typedef void(*	cy_ethif_tsu_inc_cb_t) (ETH_Type *base)
	TSU Second counter increment callback function. More...
typedef void(*	cy_ethif_rx_getbuffer_cb_t) (ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length)
	Get Buffer callback function. More...
typedef uint8_t *	cy_ethif_buffpool_t[CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE]
	Pointer to a Buffer pool.

---

Data Structure Documentation

cy_stc_ethif_wrapper_config_t

struct cy_stc_ethif_wrapper_config_t

Data Fields
cy_en_ethif_speed_sel_t	stcInterfaceSel	Interface selection for ENET.
cy_en_ethif_clock_ref_t	bRefClockSource	Reference clock selection.
uint8_t	u8RefClkDiv	Actual division would be u8RefClkDiv + 1.

cy_stc_ethif_queue_disablestatus_t

struct cy_stc_ethif_queue_disablestatus_t

Data Fields
bool	bTxQueueDisable[CY_ETH_QS2_2+1]	Tx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled.
bool	bRxQueueDisable[CY_ETH_QS2_2+1]	Rx Queue0-2 || 0: Queue Enabled, 1: Queue Disabled.

cy_stc_ethif_buff_addr_t

struct cy_stc_ethif_buff_addr_t

Data Fields
uintptr_t	vAddr	Virtual address.
uintptr_t	pAddr	Physical address.

cy_stc_ethif_bufstatus_t

struct cy_stc_ethif_bufstatus_t

Data Fields
cy_stc_ethif_buff_addr_t	cy_ethif_bufaddr	Buffer address as per requirement by Cadence driver.
cy_en_ethif_buffer_status_t	enBufStatus	Buffer status.

cy_stc_ethif_1588_timer_val_t

struct cy_stc_ethif_1588_timer_val_t

Data Fields
uint16_t	secsUpper	Upper 16 bits of seconds value.
uint32_t	secsLower	Lower 32 bits of seconds value.
uint32_t	nanosecs	Upper Nanoseconds value (30 bits)

cy_stc_ethif_timer_increment_t

struct cy_stc_ethif_timer_increment_t

Data Fields
uint8_t	nanoSecsInc	Whole nanoseconds to increment timer each clock cycle.
uint16_t	subNsInc	Sub-nanoseconds to increment the timer (16 bits)
uint8_t	lsbSubNsInc	Lower 8 bits of sub-nanoseconds to increment the timer.
uint8_t	altIncCount	Number of increments before changing to alternative increment. If = 0 then never use alternative increment.
uint8_t	altNanoSInc	Alternative nanoseconds increment to apply.

cy_stc_ethif_tsu_config_t

struct cy_stc_ethif_tsu_config_t

Data Fields
cy_stc_ethif_1588_timer_val_t *	pstcTimerValue	TSU Timer value
cy_stc_ethif_timer_increment_t *	pstcTimerIncValue	TSU Timer increment value
bool	bOneStepTxSyncEnable	One step sync enable
cy_en_ethif_TxTs_mode_t	enTxDescStoreTimeStamp	Store Time stamp value in Tx descriptor.
cy_en_ethif_RxTs_mode_t	enRxDescStoreTimeStamp	Store Time stamp value in Rx descriptor.
bool	bStoreNSinRxDesc	Store NanoSecond field of TSU in Rx Descriptor

cy_stc_ethif_cb_t

struct cy_stc_ethif_cb_t

Data Fields
cy_ethif_tx_msg_cb_t	txcompletecb	Transmit complete
cy_ethif_tx_error_cb_t	txerrorcb	Tx Error
cy_ethif_rx_frame_cb_t	rxframecb	Frame Received.
cy_ethif_tsu_inc_cb_t	tsuSecondInccb	TSU timer Second counter incremented.
cy_ethif_rx_getbuffer_cb_t	rxgetbuff	Get buffer for Receive Frame.

cy_stc_ethif_mac_config_t

struct cy_stc_ethif_mac_config_t

Data Fields
bool	bintrEnable	interrupts/events to enable on start
cy_en_ethif_dma_data_buffer_len_t	dmaDataBurstLen	fixed burst length for DMA data transfers bit4:0 amba_burst_length 1xxxx: attempt use burst up to 16 (CY_ETHIF_DMA_DBUR_LEN_16) 01xxx: attempt use burst up to 8 (CY_ETHIF_DMA_DBUR_LEN_8) 001xx: attempt use burst up to 4 (CY_ETHIF_DMA_DBUR_LEN_4) 0001x: always use single burst 00001: always use single burst (CY_ETHIF_AMBD_BURST_LEN_1) 00000: best AXI burst up to 256 beats
uint8_t	u8dmaCfgFlags	DMA config register bits 24, 25 & 26. OR the following bit-flags to set corresponding bits - CY_ETHIF_CFG_DMA_DISC_RXP, CY_ETHIF_CFG_DMA_FRCE_RX_BRST, CY_ETHIF_CFG_DMA_FRCE_TX_BRST
cy_en_ethif_dma_mdc_clk_div_t	mdcPclkDiv	divisor to generate MDC from pclk CY_ETHIF_MDC_DIV_BY_8 = 0 CY_ETHIF_MDC_DIV_BY_16 = 1 CY_ETHIF_MDC_DIV_BY_32 = 2 CY_ETHIF_MDC_DIV_BY_48 = 3 CY_ETHIF_MDC_DIV_BY_64 = 4 CY_ETHIF_MDC_DIV_BY_96 = 5 CY_ETHIF_MDC_DIV_BY_128 = 6 CY_ETHIF_MDC_DIV_BY_224 = 7
uint8_t	u8rxLenErrDisc	enable discard of frames with length field error
uint8_t	u8disCopyPause	disable copying Rx pause frames to memory
uint8_t	u8chkSumOffEn	enable checksum offload operation
uint8_t	u8rx1536ByteEn	enable Rx of frames up to 1536 bytes
uint8_t	u8rxJumboFrEn	enable Rx of jumbo frames
uint8_t	u8enRxBadPreamble	enable Rx frames with non-standard preamble
uint8_t	u8ignoreIpgRxEr	ignore IPG rx_er (NetCfg b30)
uint8_t	u8storeUdpTcpOffset	u8storeUdpTcpOffset
uint8_t	u8aw2wMaxPipeline	Maximum number of outstanding AXI write requests, that can be issued by DMA via the AW channel. Must not be = 0 if using AXI as this would disable writes
uint8_t	u8ar2rMaxPipeline	Maximum number of outstanding AXI read requests, that can be issued by DMA via the AR channel. Must not be = 0 if using AXI as this would disable reads
uint8_t	u8pfcMultiQuantum	enable pfc multiple quantum (8 different priorities)
cy_stc_ethif_wrapper_config_t *	pstcWrapperConfig	Configuration for Wrapper.
cy_stc_ethif_tsu_config_t *	pstcTSUConfig	Configuration for TSU.
bool	btxq0enable	Tx Q0 Enable
bool	btxq1enable	Tx Q1 Enable
bool	btxq2enable	Tx Q2 Enable
bool	brxq0enable	Rx Q0 Enable
bool	brxq1enable	Rx Q1 Enable
bool	brxq2enable	Rx Q2 Enable
cy_ethif_buffpool_t *	pRxQbuffPool[CY_ETH_DEFINE_NUM_RXQS]	Rx Queues buffer pool 32 bytes aligned.

cy_stc_ethif_intr_config_t

struct cy_stc_ethif_intr_config_t

Data Fields
bool	btsu_time_match	Time stamp unit time match event.
bool	bwol_rx	Wake on LAN event received.
bool	blpi_ch_rx	LPI indication status bit change received.
bool	btsu_sec_inc	TSU seconds register increment.
bool	bptp_tx_pdly_rsp	PTP pdelay_resp frame transmitted.
bool	bptp_tx_pdly_req	PTP pdelay_req frame transmitted.
bool	bptp_rx_pdly_rsp	PTP pdelay_resp frame received.
bool	bptp_rx_pdly_req	PTP pdelay_req frame received.
bool	bptp_tx_sync	PTP sync frame transmitted.
bool	bptp_tx_dly_req	PTP delay_req frame transmitted.
bool	bptp_rx_sync	PTP sync frame received.
bool	bptp_rx_dly_req	PTP delay_req frame received.
bool	bext_intr	External input interrupt detected.
bool	bpause_frame_tx	Pause frame transmitted.
bool	bpause_time_zero	Pause time reaches zero or zeroq pause frame received.
bool	bpause_nz_qu_rx	Pause frame with non-zero quantum received.
bool	bhresp_not_ok	DMA hresp not OK.
bool	brx_overrun	Rx overrun error.
bool	bpcs_link_change_det	Link status change detected by PCS.
bool	btx_complete	Frame has been transmitted successfully.
bool	btx_fr_corrupt	Tx frame corruption.
bool	btx_retry_ex_late_coll	Retry limit exceeded or late collision.
bool	btx_underrun	Tx underrun.
bool	btx_used_read	Used bit set has been read in Tx descriptor list.
bool	brx_used_read	Used bit set has been read in Rx descriptor list.
bool	brx_complete	Frame received successfully and stored.
bool	bman_frame	Management Frame Sent.

cy_stc_ethif_mac_address_t

struct cy_stc_ethif_mac_address_t

Data Fields
uint8_t	byte[6]	6 bytes MAC Address

cy_stc_ethif_filter_config_t

struct cy_stc_ethif_filter_config_t

Data Fields
cy_en_ethif_filter_type_t	typeFilter	typeFilter
cy_stc_ethif_mac_address_t	filterAddr	filterAddr
uint8_t	ignoreBytes	e.g. ignoreBytes = 0x01 implies first byte received should not be compared. e.g. ignoreBytes = 0x03 implies first and second byte received should not be compared.

Typedef Documentation

cy_ethif_tx_msg_cb_t

typedef void(* cy_ethif_tx_msg_cb_t) (ETH_Type *base, uint8_t u8QueueIndex)

Frame transmission complete callback function.

Signals a successful completed transmission.

Parameters

base[IN]	Pointer to register area of Ethernet MAC
u8Queue[IN]	Queue used for transmitting the frame

cy_ethif_tx_error_cb_t

typedef void(* cy_ethif_tx_error_cb_t) (ETH_Type *base, uint8_t u8QueueIndex)

Frame transmission Error callback function.

Signals a transmission error.

Parameters

base[IN]	Pointer to register area of Ethernet MAC
u8Queue[IN]	Queue used for transmitting the frame

cy_ethif_rx_frame_cb_t

typedef void(* cy_ethif_rx_frame_cb_t) (ETH_Type *base, uint8_t *u8RxBuffer, uint32_t u32Length)

Frame received callback function.

Signals a successful reception of frame.

Parameters

base[IN]	Pointer to register area of Ethernet MAC
u8RxBuffer[IN]	Receive frame buffer
u32Length[IN]	Frame buffer length

cy_ethif_tsu_inc_cb_t

typedef void(* cy_ethif_tsu_inc_cb_t) (ETH_Type *base)

TSU Second counter increment callback function.

Signals a One second increment in the TSU.

Parameters

base[IN]

Pointer to register area of Ethernet MAC

cy_ethif_rx_getbuffer_cb_t

typedef void(* cy_ethif_rx_getbuffer_cb_t) (ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length)

Get Buffer callback function.

Driver call this for getting free buffer for filling subsequent receive frame.

Parameters

base[IN]	Pointer to register area of Ethernet MAC
u8RxBuffer[OUT]	32 bytes aligned Frame buffer
u32Length[OUT]	Frame buffer length