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PSOC E8XXGP Device Support Library
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PSOC E8XXGP Device Support Library
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Ethernet Interface (ETH)
Data Fields | |
| __IOM uint32_t | CTL |
| __IM uint32_t | STATUS |
| __IM uint32_t | RESERVED [1022] |
| __IOM uint32_t | NETWORK_CONTROL |
| __IOM uint32_t | NETWORK_CONFIG |
| __IM uint32_t | NETWORK_STATUS |
| __IM uint32_t | USER_IO_REGISTER |
| __IOM uint32_t | DMA_CONFIG |
| __IOM uint32_t | TRANSMIT_STATUS |
| __IOM uint32_t | RECEIVE_Q_PTR |
| __IOM uint32_t | TRANSMIT_Q_PTR |
| __IOM uint32_t | RECEIVE_STATUS |
| __IOM uint32_t | INT_STATUS |
| __OM uint32_t | INT_ENABLE |
| __IOM uint32_t | INT_DISABLE |
| __IM uint32_t | INT_MASK |
| __IOM uint32_t | PHY_MANAGEMENT |
| __IM uint32_t | PAUSE_TIME |
| __IOM uint32_t | TX_PAUSE_QUANTUM |
| __IOM uint32_t | PBUF_TXCUTTHRU |
| __IOM uint32_t | PBUF_RXCUTTHRU |
| __IOM uint32_t | JUMBO_MAX_LENGTH |
| __IM uint32_t | EXTERNAL_FIFO_INTERFACE |
| __IM uint32_t | RESERVED1 |
| __IOM uint32_t | AXI_MAX_PIPELINE |
| __IM uint32_t | RSC_CONTROL |
| __IOM uint32_t | INT_MODERATION |
| __IOM uint32_t | SYS_WAKE_TIME |
| __IM uint32_t | RESERVED2 [7] |
| __IOM uint32_t | HASH_BOTTOM |
| __IOM uint32_t | HASH_TOP |
| __IOM uint32_t | SPEC_ADD1_BOTTOM |
| __IOM uint32_t | SPEC_ADD1_TOP |
| __IOM uint32_t | SPEC_ADD2_BOTTOM |
| __IOM uint32_t | SPEC_ADD2_TOP |
| __IOM uint32_t | SPEC_ADD3_BOTTOM |
| __IOM uint32_t | SPEC_ADD3_TOP |
| __IOM uint32_t | SPEC_ADD4_BOTTOM |
| __IOM uint32_t | SPEC_ADD4_TOP |
| __IOM uint32_t | SPEC_TYPE1 |
| __IOM uint32_t | SPEC_TYPE2 |
| __IOM uint32_t | SPEC_TYPE3 |
| __IOM uint32_t | SPEC_TYPE4 |
| __IOM uint32_t | WOL_REGISTER |
| __IOM uint32_t | STRETCH_RATIO |
| __IOM uint32_t | STACKED_VLAN |
| __IOM uint32_t | TX_PFC_PAUSE |
| __IOM uint32_t | MASK_ADD1_BOTTOM |
| __IOM uint32_t | MASK_ADD1_TOP |
| __IOM uint32_t | DMA_ADDR_OR_MASK |
| __IOM uint32_t | RX_PTP_UNICAST |
| __IOM uint32_t | TX_PTP_UNICAST |
| __IOM uint32_t | TSU_NSEC_CMP |
| __IOM uint32_t | TSU_SEC_CMP |
| __IOM uint32_t | TSU_MSB_SEC_CMP |
| __IM uint32_t | TSU_PTP_TX_MSB_SEC |
| __IM uint32_t | TSU_PTP_RX_MSB_SEC |
| __IM uint32_t | TSU_PEER_TX_MSB_SEC |
| __IM uint32_t | TSU_PEER_RX_MSB_SEC |
| __IOM uint32_t | DPRAM_FILL_DBG |
| __IM uint32_t | REVISION_REG |
| __IM uint32_t | OCTETS_TXED_BOTTOM |
| __IM uint32_t | OCTETS_TXED_TOP |
| __IM uint32_t | FRAMES_TXED_OK |
| __IM uint32_t | BROADCAST_TXED |
| __IM uint32_t | MULTICAST_TXED |
| __IM uint32_t | PAUSE_FRAMES_TXED |
| __IM uint32_t | FRAMES_TXED_64 |
| __IM uint32_t | FRAMES_TXED_65 |
| __IM uint32_t | FRAMES_TXED_128 |
| __IM uint32_t | FRAMES_TXED_256 |
| __IM uint32_t | FRAMES_TXED_512 |
| __IM uint32_t | FRAMES_TXED_1024 |
| __IM uint32_t | FRAMES_TXED_1519 |
| __IM uint32_t | TX_UNDERRUNS |
| __IM uint32_t | SINGLE_COLLISIONS |
| __IM uint32_t | MULTIPLE_COLLISIONS |
| __IM uint32_t | EXCESSIVE_COLLISIONS |
| __IM uint32_t | LATE_COLLISIONS |
| __IM uint32_t | DEFERRED_FRAMES |
| __IM uint32_t | CRS_ERRORS |
| __IM uint32_t | OCTETS_RXED_BOTTOM |
| __IM uint32_t | OCTETS_RXED_TOP |
| __IM uint32_t | FRAMES_RXED_OK |
| __IM uint32_t | BROADCAST_RXED |
| __IM uint32_t | MULTICAST_RXED |
| __IM uint32_t | PAUSE_FRAMES_RXED |
| __IM uint32_t | FRAMES_RXED_64 |
| __IM uint32_t | FRAMES_RXED_65 |
| __IM uint32_t | FRAMES_RXED_128 |
| __IM uint32_t | FRAMES_RXED_256 |
| __IM uint32_t | FRAMES_RXED_512 |
| __IM uint32_t | FRAMES_RXED_1024 |
| __IM uint32_t | FRAMES_RXED_1519 |
| __IM uint32_t | UNDERSIZE_FRAMES |
| __IM uint32_t | EXCESSIVE_RX_LENGTH |
| __IM uint32_t | RX_JABBERS |
| __IM uint32_t | FCS_ERRORS |
| __IM uint32_t | RX_LENGTH_ERRORS |
| __IM uint32_t | RX_SYMBOL_ERRORS |
| __IM uint32_t | ALIGNMENT_ERRORS |
| __IM uint32_t | RX_RESOURCE_ERRORS |
| __IM uint32_t | RX_OVERRUNS |
| __IM uint32_t | RX_IP_CK_ERRORS |
| __IM uint32_t | RX_TCP_CK_ERRORS |
| __IM uint32_t | RX_UDP_CK_ERRORS |
| __IM uint32_t | AUTO_FLUSHED_PKTS |
| __IM uint32_t | RESERVED3 |
| __IOM uint32_t | TSU_TIMER_INCR_SUB_NSEC |
| __IOM uint32_t | TSU_TIMER_MSB_SEC |
| __IM uint32_t | TSU_STROBE_MSB_SEC |
| __IM uint32_t | TSU_STROBE_SEC |
| __IM uint32_t | TSU_STROBE_NSEC |
| __IOM uint32_t | TSU_TIMER_SEC |
| __IOM uint32_t | TSU_TIMER_NSEC |
| __OM uint32_t | TSU_TIMER_ADJUST |
| __IOM uint32_t | TSU_TIMER_INCR |
| __IM uint32_t | TSU_PTP_TX_SEC |
| __IM uint32_t | TSU_PTP_TX_NSEC |
| __IM uint32_t | TSU_PTP_RX_SEC |
| __IM uint32_t | TSU_PTP_RX_NSEC |
| __IM uint32_t | TSU_PEER_TX_SEC |
| __IM uint32_t | TSU_PEER_TX_NSEC |
| __IM uint32_t | TSU_PEER_RX_SEC |
| __IM uint32_t | TSU_PEER_RX_NSEC |
| __IM uint32_t | PCS_CONTROL |
| __IM uint32_t | PCS_STATUS |
| __IM uint32_t | RESERVED4 [2] |
| __IM uint32_t | PCS_AN_ADV |
| __IM uint32_t | PCS_AN_LP_BASE |
| __IM uint32_t | PCS_AN_EXP |
| __IM uint32_t | PCS_AN_NP_TX |
| __IM uint32_t | PCS_AN_LP_NP |
| __IM uint32_t | RESERVED5 [6] |
| __IM uint32_t | PCS_AN_EXT_STATUS |
| __IM uint32_t | RESERVED6 [8] |
| __IOM uint32_t | TX_PAUSE_QUANTUM1 |
| __IOM uint32_t | TX_PAUSE_QUANTUM2 |
| __IOM uint32_t | TX_PAUSE_QUANTUM3 |
| __IM uint32_t | RESERVED7 |
| __IM uint32_t | RX_LPI |
| __IM uint32_t | RX_LPI_TIME |
| __IM uint32_t | TX_LPI |
| __IM uint32_t | TX_LPI_TIME |
| __IM uint32_t | DESIGNCFG_DEBUG1 |
| __IM uint32_t | DESIGNCFG_DEBUG2 |
| __IM uint32_t | DESIGNCFG_DEBUG3 |
| __IM uint32_t | DESIGNCFG_DEBUG4 |
| __IM uint32_t | DESIGNCFG_DEBUG5 |
| __IM uint32_t | DESIGNCFG_DEBUG6 |
| __IM uint32_t | DESIGNCFG_DEBUG7 |
| __IM uint32_t | DESIGNCFG_DEBUG8 |
| __IM uint32_t | DESIGNCFG_DEBUG9 |
| __IM uint32_t | DESIGNCFG_DEBUG10 |
| __IM uint32_t | RESERVED8 [22] |
| __IM uint32_t | SPEC_ADD5_BOTTOM |
| __IM uint32_t | SPEC_ADD5_TOP |
| __IM uint32_t | RESERVED9 [60] |
| __IM uint32_t | SPEC_ADD36_BOTTOM |
| __IM uint32_t | SPEC_ADD36_TOP |
| __IM uint32_t | INT_Q1_STATUS |
| __IM uint32_t | INT_Q2_STATUS |
| __IM uint32_t | INT_Q3_STATUS |
| __IM uint32_t | RESERVED10 [11] |
| __IM uint32_t | INT_Q15_STATUS |
| __IM uint32_t | RESERVED11 |
| __IOM uint32_t | TRANSMIT_Q1_PTR |
| __IOM uint32_t | TRANSMIT_Q2_PTR |
| __IM uint32_t | TRANSMIT_Q3_PTR |
| __IM uint32_t | RESERVED12 [11] |
| __IM uint32_t | TRANSMIT_Q15_PTR |
| __IM uint32_t | RESERVED13 |
| __IOM uint32_t | RECEIVE_Q1_PTR |
| __IOM uint32_t | RECEIVE_Q2_PTR |
| __IM uint32_t | RECEIVE_Q3_PTR |
| __IM uint32_t | RESERVED14 [3] |
| __IM uint32_t | RECEIVE_Q7_PTR |
| __IM uint32_t | RESERVED15 |
| __IOM uint32_t | DMA_RXBUF_SIZE_Q1 |
| __IOM uint32_t | DMA_RXBUF_SIZE_Q2 |
| __IM uint32_t | DMA_RXBUF_SIZE_Q3 |
| __IM uint32_t | RESERVED16 [3] |
| __IM uint32_t | DMA_RXBUF_SIZE_Q7 |
| __IOM uint32_t | CBS_CONTROL |
| __IOM uint32_t | CBS_IDLESLOPE_Q_A |
| __IOM uint32_t | CBS_IDLESLOPE_Q_B |
| __IOM uint32_t | UPPER_TX_Q_BASE_ADDR |
| __IOM uint32_t | TX_BD_CONTROL |
| __IOM uint32_t | RX_BD_CONTROL |
| __IOM uint32_t | UPPER_RX_Q_BASE_ADDR |
| __IM uint32_t | RESERVED17 [2] |
| __IOM uint32_t | HIDDEN_REG0 |
| __IOM uint32_t | HIDDEN_REG1 |
| __IOM uint32_t | HIDDEN_REG2 |
| __IOM uint32_t | HIDDEN_REG3 |
| __IM uint32_t | RESERVED18 [2] |
| __IOM uint32_t | HIDDEN_REG4 |
| __IOM uint32_t | HIDDEN_REG5 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_0 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_1 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_2 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_3 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_4 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_5 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_6 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_7 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_8 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_9 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_10 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_11 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_12 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_13 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_14 |
| __IOM uint32_t | SCREENING_TYPE_1_REGISTER_15 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_0 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_1 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_2 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_3 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_4 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_5 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_6 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_7 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_8 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_9 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_10 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_11 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_12 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_13 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_14 |
| __IOM uint32_t | SCREENING_TYPE_2_REGISTER_15 |
| __IOM uint32_t | TX_SCHED_CTRL |
| __IM uint32_t | RESERVED19 [3] |
| __IOM uint32_t | BW_RATE_LIMIT_Q0TO3 |
| __IOM uint32_t | BW_RATE_LIMIT_Q4TO7 |
| __IM uint32_t | BW_RATE_LIMIT_Q8TO11 |
| __IM uint32_t | BW_RATE_LIMIT_Q12TO15 |
| __IOM uint32_t | TX_Q_SEG_ALLOC_Q0TO7 |
| __IM uint32_t | TX_Q_SEG_ALLOC_Q8TO15 |
| __IM uint32_t | RESERVED20 [6] |
| __IM uint32_t | RECEIVE_Q8_PTR |
| __IM uint32_t | RESERVED21 [6] |
| __IM uint32_t | RECEIVE_Q15_PTR |
| __IM uint32_t | DMA_RXBUF_SIZE_Q8 |
| __IM uint32_t | RESERVED22 [6] |
| __IM uint32_t | DMA_RXBUF_SIZE_Q15 |
| __OM uint32_t | INT_Q1_ENABLE |
| __OM uint32_t | INT_Q2_ENABLE |
| __IM uint32_t | INT_Q3_ENABLE |
| __IM uint32_t | RESERVED23 [3] |
| __IM uint32_t | INT_Q7_ENABLE |
| __IM uint32_t | RESERVED24 |
| __OM uint32_t | INT_Q1_DISABLE |
| __OM uint32_t | INT_Q2_DISABLE |
| __IM uint32_t | INT_Q3_DISABLE |
| __IM uint32_t | RESERVED25 [3] |
| __IM uint32_t | INT_Q7_DISABLE |
| __IM uint32_t | RESERVED26 |
| __IM uint32_t | INT_Q1_MASK |
| __IM uint32_t | INT_Q2_MASK |
| __IM uint32_t | INT_Q3_MASK |
| __IM uint32_t | RESERVED27 [3] |
| __IM uint32_t | INT_Q7_MASK |
| __IM uint32_t | RESERVED28 |
| __IM uint32_t | INT_Q8_ENABLE |
| __IM uint32_t | RESERVED29 [6] |
| __IM uint32_t | INT_Q15_ENABLE |
| __IM uint32_t | INT_Q8_DISABLE |
| __IM uint32_t | RESERVED30 [6] |
| __IM uint32_t | INT_Q15_DISABLE |
| __IM uint32_t | INT_Q8_MASK |
| __IM uint32_t | RESERVED31 [6] |
| __IM uint32_t | INT_Q15_MASK |
| __IM uint32_t | RESERVED32 [8] |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_0 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_1 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_2 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_3 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_4 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_5 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_6 |
| __IOM uint32_t | SCREENING_TYPE_2_ETHERTYPE_REG_7 |
| __IOM uint32_t | TYPE2_COMPARE_0_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_0_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_1_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_1_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_2_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_2_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_3_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_3_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_4_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_4_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_5_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_5_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_6_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_6_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_7_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_7_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_8_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_8_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_9_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_9_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_10_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_10_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_11_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_11_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_12_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_12_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_13_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_13_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_14_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_14_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_15_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_15_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_16_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_16_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_17_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_17_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_18_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_18_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_19_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_19_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_20_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_20_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_21_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_21_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_22_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_22_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_23_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_23_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_24_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_24_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_25_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_25_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_26_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_26_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_27_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_27_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_28_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_28_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_29_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_29_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_30_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_30_WORD_1 |
| __IOM uint32_t | TYPE2_COMPARE_31_WORD_0 |
| __IOM uint32_t | TYPE2_COMPARE_31_WORD_1 |
| __IOM uint32_t ETH_Type::CTL |
0x00000000 EMAC Control Register
| __IM uint32_t ETH_Type::STATUS |
0x00000004 EMAC Status Register
| __IM uint32_t ETH_Type::RESERVED[1022] |
| __IOM uint32_t ETH_Type::NETWORK_CONTROL |
0x00001000 The network control register contains general MAC control functions for both receiver and transmitter.
| __IOM uint32_t ETH_Type::NETWORK_CONFIG |
0x00001004 The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.
| __IM uint32_t ETH_Type::NETWORK_STATUS |
0x00001008 The network status register returns status information with respect to the PHY management interface.
| __IM uint32_t ETH_Type::USER_IO_REGISTER |
0x0000100C Not presents. Access to the register will return AHB error.
| __IOM uint32_t ETH_Type::DMA_CONFIG |
0x00001010 DMA Configuration Register
| __IOM uint32_t ETH_Type::TRANSMIT_STATUS |
0x00001014 This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
| __IOM uint32_t ETH_Type::RECEIVE_Q_PTR |
0x00001018 This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AXI) operation, the receive descriptors are read from memory using a single 32bit AXI access. When the datapath is configured at 64bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AXI access.
| __IOM uint32_t ETH_Type::TRANSMIT_Q_PTR |
0x0000101C This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access.
| __IOM uint32_t ETH_Type::RECEIVE_STATUS |
0x00001020 This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
| __IOM uint32_t ETH_Type::INT_STATUS |
0x00001024 If not configured for priority queueing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no affect on the status of the bit.
| __OM uint32_t ETH_Type::INT_ENABLE |
0x00001028 At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
| __IOM uint32_t ETH_Type::INT_DISABLE |
0x0000102C Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
| __IM uint32_t ETH_Type::INT_MASK |
0x00001030 The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
| __IOM uint32_t ETH_Type::PHY_MANAGEMENT |
0x00001034 The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register.
| __IM uint32_t ETH_Type::PAUSE_TIME |
0x00001038 Received Pause Quantum Register
| __IOM uint32_t ETH_Type::TX_PAUSE_QUANTUM |
0x0000103C Transmit Pause Quantum Register
| __IOM uint32_t ETH_Type::PBUF_TXCUTTHRU |
0x00001040 Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward
| __IOM uint32_t ETH_Type::PBUF_RXCUTTHRU |
0x00001044 RX Partial Store and Forward
| __IOM uint32_t ETH_Type::JUMBO_MAX_LENGTH |
0x00001048 Maximum Jumbo Frame Size.
| __IM uint32_t ETH_Type::EXTERNAL_FIFO_INTERFACE |
0x0000104C Not presents.
| __IM uint32_t ETH_Type::RESERVED1 |
| __IOM uint32_t ETH_Type::AXI_MAX_PIPELINE |
0x00001054 Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)
| __IM uint32_t ETH_Type::RSC_CONTROL |
0x00001058 Not presents. Access to the register will return AHB error.
| __IOM uint32_t ETH_Type::INT_MODERATION |
0x0000105C Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation.
| __IOM uint32_t ETH_Type::SYS_WAKE_TIME |
0x00001060 Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time.
| __IM uint32_t ETH_Type::RESERVED2[7] |
| __IOM uint32_t ETH_Type::HASH_BOTTOM |
0x00001080 The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits)
| __IOM uint32_t ETH_Type::HASH_TOP |
0x00001084 Hash Register Top (63 to 32 bits)
| __IOM uint32_t ETH_Type::SPEC_ADD1_BOTTOM |
0x00001088 The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
| __IOM uint32_t ETH_Type::SPEC_ADD1_TOP |
0x0000108C Specific Address Top
| __IOM uint32_t ETH_Type::SPEC_ADD2_BOTTOM |
0x00001090 The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
| __IOM uint32_t ETH_Type::SPEC_ADD2_TOP |
0x00001094 Specific Address Top
| __IOM uint32_t ETH_Type::SPEC_ADD3_BOTTOM |
0x00001098 The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
| __IOM uint32_t ETH_Type::SPEC_ADD3_TOP |
0x0000109C Specific Address Top
| __IOM uint32_t ETH_Type::SPEC_ADD4_BOTTOM |
0x000010A0 The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
| __IOM uint32_t ETH_Type::SPEC_ADD4_TOP |
0x000010A4 Specific Address Top
| __IOM uint32_t ETH_Type::SPEC_TYPE1 |
0x000010A8 Type ID Match 1
| __IOM uint32_t ETH_Type::SPEC_TYPE2 |
0x000010AC Type ID Match 2
| __IOM uint32_t ETH_Type::SPEC_TYPE3 |
0x000010B0 Type ID Match 3
| __IOM uint32_t ETH_Type::SPEC_TYPE4 |
0x000010B4 Type ID Match 4
| __IOM uint32_t ETH_Type::WOL_REGISTER |
0x000010B8 Wake on LAN Register. Presents in design, but feature is not supported.
| __IOM uint32_t ETH_Type::STRETCH_RATIO |
0x000010BC IPG stretch register
| __IOM uint32_t ETH_Type::STACKED_VLAN |
0x000010C0 Stacked VLAN Register
| __IOM uint32_t ETH_Type::TX_PFC_PAUSE |
0x000010C4 Transmit PFC Pause Register
| __IOM uint32_t ETH_Type::MASK_ADD1_BOTTOM |
0x000010C8 Specific Address Mask 1 Bottom (31 to 0 bits)
| __IOM uint32_t ETH_Type::MASK_ADD1_TOP |
0x000010CC Specific Address Mask 1 Top (47 to 32 bits)
| __IOM uint32_t ETH_Type::DMA_ADDR_OR_MASK |
0x000010D0 Receive DMA Data Buffer Address Mask
| __IOM uint32_t ETH_Type::RX_PTP_UNICAST |
0x000010D4 PTP RX unicast IP destination address
| __IOM uint32_t ETH_Type::TX_PTP_UNICAST |
0x000010D8 PTP TX unicast IP destination address
| __IOM uint32_t ETH_Type::TSU_NSEC_CMP |
0x000010DC TSU timer comparison value nanoseconds
| __IOM uint32_t ETH_Type::TSU_SEC_CMP |
0x000010E0 TSU timer comparison value seconds (31 to 0 bits)
| __IOM uint32_t ETH_Type::TSU_MSB_SEC_CMP |
0x000010E4 TSU timer comparison value seconds (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_PTP_TX_MSB_SEC |
0x000010E8 PTP Event Frame Transmitted Seconds Register (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_PTP_RX_MSB_SEC |
0x000010EC PTP Event Frame Received Seconds Register (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_PEER_TX_MSB_SEC |
0x000010F0 PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_PEER_RX_MSB_SEC |
0x000010F4 PTP Peer Event Frame Received Seconds Register (47 to 32 bits)
| __IOM uint32_t ETH_Type::DPRAM_FILL_DBG |
0x000010F8 The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction.
| __IM uint32_t ETH_Type::REVISION_REG |
0x000010FC This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value
| __IM uint32_t ETH_Type::OCTETS_TXED_BOTTOM |
0x00001100 Octets Transmitted lower bits (31 to 0 bits)
| __IM uint32_t ETH_Type::OCTETS_TXED_TOP |
0x00001104 Octets Transmitted higher bits (47 to 32 bits)
| __IM uint32_t ETH_Type::FRAMES_TXED_OK |
0x00001108 Frames Transmitted
| __IM uint32_t ETH_Type::BROADCAST_TXED |
0x0000110C Broadcast Frames Transmitted
| __IM uint32_t ETH_Type::MULTICAST_TXED |
0x00001110 Multicast Frames Transmitted
| __IM uint32_t ETH_Type::PAUSE_FRAMES_TXED |
0x00001114 Pause Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_64 |
0x00001118 64 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_65 |
0x0000111C 65 to 127 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_128 |
0x00001120 128 to 255 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_256 |
0x00001124 256 to 511 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_512 |
0x00001128 512 to 1023 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_1024 |
0x0000112C 1024 to 1518 Byte Frames Transmitted
| __IM uint32_t ETH_Type::FRAMES_TXED_1519 |
0x00001130 Greater Than 1518 Byte Frames Transmitted
| __IM uint32_t ETH_Type::TX_UNDERRUNS |
0x00001134 Transmit Under Runs
| __IM uint32_t ETH_Type::SINGLE_COLLISIONS |
0x00001138 Single Collision Frames. Presents in design but not support.
| __IM uint32_t ETH_Type::MULTIPLE_COLLISIONS |
0x0000113C Multiple Collision Frames. Presents in design but not support.
| __IM uint32_t ETH_Type::EXCESSIVE_COLLISIONS |
0x00001140 Excessive Collisions. Presents in design but not support.
| __IM uint32_t ETH_Type::LATE_COLLISIONS |
0x00001144 Late Collisions. Presents in design but not support.
| __IM uint32_t ETH_Type::DEFERRED_FRAMES |
0x00001148 Deferred Transmission Frames. Presents in design but not support.
| __IM uint32_t ETH_Type::CRS_ERRORS |
0x0000114C Carrier Sense Errors. Presents in design but not support.
| __IM uint32_t ETH_Type::OCTETS_RXED_BOTTOM |
0x00001150 Octets Received (31 to 0 bits)
| __IM uint32_t ETH_Type::OCTETS_RXED_TOP |
0x00001154 Octets Received (47 to 32 bits)
| __IM uint32_t ETH_Type::FRAMES_RXED_OK |
0x00001158 Frames Received
| __IM uint32_t ETH_Type::BROADCAST_RXED |
0x0000115C Broadcast Frames Received
| __IM uint32_t ETH_Type::MULTICAST_RXED |
0x00001160 Multicast Frames Received
| __IM uint32_t ETH_Type::PAUSE_FRAMES_RXED |
0x00001164 Pause Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_64 |
0x00001168 64 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_65 |
0x0000116C 65 to 127 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_128 |
0x00001170 128 to 255 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_256 |
0x00001174 256 to 511 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_512 |
0x00001178 512 to 1023 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_1024 |
0x0000117C 1024 to 1518 Byte Frames Received
| __IM uint32_t ETH_Type::FRAMES_RXED_1519 |
0x00001180 1519 to maximum Byte Frames Received
| __IM uint32_t ETH_Type::UNDERSIZE_FRAMES |
0x00001184 Undersized Frames Received
| __IM uint32_t ETH_Type::EXCESSIVE_RX_LENGTH |
0x00001188 Oversize Frames Received
| __IM uint32_t ETH_Type::RX_JABBERS |
0x0000118C Jabbers Received
| __IM uint32_t ETH_Type::FCS_ERRORS |
0x00001190 Frame Check Sequence Errors
| __IM uint32_t ETH_Type::RX_LENGTH_ERRORS |
0x00001194 Length Field Frame Errors
| __IM uint32_t ETH_Type::RX_SYMBOL_ERRORS |
0x00001198 Receive Symbol Errors
| __IM uint32_t ETH_Type::ALIGNMENT_ERRORS |
0x0000119C Alignment Errors
| __IM uint32_t ETH_Type::RX_RESOURCE_ERRORS |
0x000011A0 Receive Resource Errors
| __IM uint32_t ETH_Type::RX_OVERRUNS |
0x000011A4 Receive Overruns
| __IM uint32_t ETH_Type::RX_IP_CK_ERRORS |
0x000011A8 IP Header Checksum Errors
| __IM uint32_t ETH_Type::RX_TCP_CK_ERRORS |
0x000011AC TCP Checksum Errors
| __IM uint32_t ETH_Type::RX_UDP_CK_ERRORS |
0x000011B0 UDP Checksum Errors
| __IM uint32_t ETH_Type::AUTO_FLUSHED_PKTS |
0x000011B4 Receive DMA Flushed Packets
| __IM uint32_t ETH_Type::RESERVED3 |
| __IOM uint32_t ETH_Type::TSU_TIMER_INCR_SUB_NSEC |
0x000011BC 1588 Timer Increment Register sub nsec
| __IOM uint32_t ETH_Type::TSU_TIMER_MSB_SEC |
0x000011C0 1588 Timer Seconds Register (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_STROBE_MSB_SEC |
0x000011C4 1588 Timer Sync Strobe Seconds Register (47 to 32 bits)
| __IM uint32_t ETH_Type::TSU_STROBE_SEC |
0x000011C8 1588 Timer Sync Strobe Seconds Register (31 to 0 bits)
| __IM uint32_t ETH_Type::TSU_STROBE_NSEC |
0x000011CC 1588 Timer Sync Strobe Nanoseconds Register
| __IOM uint32_t ETH_Type::TSU_TIMER_SEC |
0x000011D0 1588 Timer Seconds Register (31 to 0 bits)
| __IOM uint32_t ETH_Type::TSU_TIMER_NSEC |
0x000011D4 1588 Timer Nanoseconds Register
| __OM uint32_t ETH_Type::TSU_TIMER_ADJUST |
0x000011D8 This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read.
| __IOM uint32_t ETH_Type::TSU_TIMER_INCR |
0x000011DC 1588 Timer Increment Register
| __IM uint32_t ETH_Type::TSU_PTP_TX_SEC |
0x000011E0 PTP Event Frame Transmitted Seconds Register (31 to 0 bits)
| __IM uint32_t ETH_Type::TSU_PTP_TX_NSEC |
0x000011E4 PTP Event Frame Transmitted Nanoseconds Register
| __IM uint32_t ETH_Type::TSU_PTP_RX_SEC |
0x000011E8 PTP Event Frame Received Seconds Register (31 to 0 bits)
| __IM uint32_t ETH_Type::TSU_PTP_RX_NSEC |
0x000011EC PTP Event Frame Received Nanoseconds Register
| __IM uint32_t ETH_Type::TSU_PEER_TX_SEC |
0x000011F0 PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)
| __IM uint32_t ETH_Type::TSU_PEER_TX_NSEC |
0x000011F4 PTP Peer Event Frame Transmitted Nanoseconds Register
| __IM uint32_t ETH_Type::TSU_PEER_RX_SEC |
0x000011F8 PTP Peer Event Frame Received Seconds Register (31 to 0 bits)
| __IM uint32_t ETH_Type::TSU_PEER_RX_NSEC |
0x000011FC PTP Peer Event Frame Received Nanoseconds Register
| __IM uint32_t ETH_Type::PCS_CONTROL |
0x00001200 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::PCS_STATUS |
0x00001204 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED4[2] |
| __IM uint32_t ETH_Type::PCS_AN_ADV |
0x00001210 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::PCS_AN_LP_BASE |
0x00001214 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::PCS_AN_EXP |
0x00001218 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::PCS_AN_NP_TX |
0x0000121C Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::PCS_AN_LP_NP |
0x00001220 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED5[6] |
| __IM uint32_t ETH_Type::PCS_AN_EXT_STATUS |
0x0000123C Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED6[8] |
| __IOM uint32_t ETH_Type::TX_PAUSE_QUANTUM1 |
0x00001260 Transmit Pause Quantum Register 1
| __IOM uint32_t ETH_Type::TX_PAUSE_QUANTUM2 |
0x00001264 Transmit Pause Quantum Register 2
| __IOM uint32_t ETH_Type::TX_PAUSE_QUANTUM3 |
0x00001268 Transmit Pause Quantum Register 3
| __IM uint32_t ETH_Type::RESERVED7 |
| __IM uint32_t ETH_Type::RX_LPI |
0x00001270 Received LPI transitions
| __IM uint32_t ETH_Type::RX_LPI_TIME |
0x00001274 Received LPI time
| __IM uint32_t ETH_Type::TX_LPI |
0x00001278 Transmit LPI transitions
| __IM uint32_t ETH_Type::TX_LPI_TIME |
0x0000127C Transmit LPI time
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG1 |
0x00001280 Design Configuration Register 1
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG2 |
0x00001284 Design Configuration Register 2
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG3 |
0x00001288 Design Configuration Register 3
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG4 |
0x0000128C Design Configuration Register 4
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG5 |
0x00001290 Design Configuration Register 5
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG6 |
0x00001294 Design Configuration Register 6
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG7 |
0x00001298 Design Configuration Register 7
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG8 |
0x0000129C Design Configuration Register 8
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG9 |
0x000012A0 Design Configuration Register 9
| __IM uint32_t ETH_Type::DESIGNCFG_DEBUG10 |
0x000012A4 Design Configuration Register 10
| __IM uint32_t ETH_Type::RESERVED8[22] |
| __IM uint32_t ETH_Type::SPEC_ADD5_BOTTOM |
0x00001300 Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::SPEC_ADD5_TOP |
0x00001304 Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED9[60] |
| __IM uint32_t ETH_Type::SPEC_ADD36_BOTTOM |
0x000013F8 Not presents.
| __IM uint32_t ETH_Type::SPEC_ADD36_TOP |
0x000013FC Not presents.
| __IM uint32_t ETH_Type::INT_Q1_STATUS |
0x00001400 Priority queue Interrupt Status Register
| __IM uint32_t ETH_Type::INT_Q2_STATUS |
0x00001404 Priority queue Interrupt Status Register
| __IM uint32_t ETH_Type::INT_Q3_STATUS |
0x00001408 int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED10[11] |
| __IM uint32_t ETH_Type::INT_Q15_STATUS |
0x00001438 Not presents.
| __IM uint32_t ETH_Type::RESERVED11 |
| __IOM uint32_t ETH_Type::TRANSMIT_Q1_PTR |
0x00001440 This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access.
| __IOM uint32_t ETH_Type::TRANSMIT_Q2_PTR |
0x00001444 This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access.
| __IM uint32_t ETH_Type::TRANSMIT_Q3_PTR |
0x00001448 transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED12[11] |
| __IM uint32_t ETH_Type::TRANSMIT_Q15_PTR |
0x00001478 Not presents.
| __IM uint32_t ETH_Type::RESERVED13 |
| __IOM uint32_t ETH_Type::RECEIVE_Q1_PTR |
0x00001480 This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access.
| __IOM uint32_t ETH_Type::RECEIVE_Q2_PTR |
0x00001484 This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access.
| __IM uint32_t ETH_Type::RECEIVE_Q3_PTR |
0x00001488 Not presents. Start address register doesn't present for queue3 ~ queue7.
| __IM uint32_t ETH_Type::RESERVED14[3] |
| __IM uint32_t ETH_Type::RECEIVE_Q7_PTR |
0x00001498 Not presents.
| __IM uint32_t ETH_Type::RESERVED15 |
| __IOM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q1 |
0x000014A0 Receive Buffer queue 1 Size
| __IOM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q2 |
0x000014A4 Receive Buffer queue 2 Size
| __IM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q3 |
0x000014A8 dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present.
| __IM uint32_t ETH_Type::RESERVED16[3] |
| __IM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q7 |
0x000014B8 Not presents.
| __IOM uint32_t ETH_Type::CBS_CONTROL |
0x000014BC The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note that Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved.
| __IOM uint32_t ETH_Type::CBS_IDLESLOPE_Q_A |
0x000014C0 queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration.
| __IOM uint32_t ETH_Type::CBS_IDLESLOPE_Q_B |
0x000014C4 queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration.
| __IOM uint32_t ETH_Type::UPPER_TX_Q_BASE_ADDR |
0x000014C8 Upper 32 bits of transmit buffer descriptor queue base address.
| __IOM uint32_t ETH_Type::TX_BD_CONTROL |
0x000014CC TX BD control register
| __IOM uint32_t ETH_Type::RX_BD_CONTROL |
0x000014D0 RX BD control register
| __IOM uint32_t ETH_Type::UPPER_RX_Q_BASE_ADDR |
0x000014D4 Upper 32 bits of receive buffer descriptor queue base address.
| __IM uint32_t ETH_Type::RESERVED17[2] |
| __IOM uint32_t ETH_Type::HIDDEN_REG0 |
0x000014E0 Hidden register
| __IOM uint32_t ETH_Type::HIDDEN_REG1 |
0x000014E4 Hidden register
| __IOM uint32_t ETH_Type::HIDDEN_REG2 |
0x000014E8 Hidden register
| __IOM uint32_t ETH_Type::HIDDEN_REG3 |
0x000014EC Hidden register
| __IM uint32_t ETH_Type::RESERVED18[2] |
| __IOM uint32_t ETH_Type::HIDDEN_REG4 |
0x000014F8 Hidden register
| __IOM uint32_t ETH_Type::HIDDEN_REG5 |
0x000014FC Hidden register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_0 |
0x00001500 Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11 to 4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27 to 12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 2 to 0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_1 |
0x00001504 screening type 1 register 1, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_2 |
0x00001508 screening type 1 register 2, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_3 |
0x0000150C screening type 1 register 3, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_4 |
0x00001510 screening type 1 register 4, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_5 |
0x00001514 screening type 1 register 5, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_6 |
0x00001518 screening type 1 register 6, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_7 |
0x0000151C screening type 1 register 7, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_8 |
0x00001520 screening type 1 register 8, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_9 |
0x00001524 screening type 1 register 9, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_10 |
0x00001528 screening type 1 register 10, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_11 |
0x0000152C screening type 1 register 11, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_12 |
0x00001530 screening type 1 register 12, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_13 |
0x00001534 screening type 1 register 13, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_14 |
0x00001538 screening type 1 register 14, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_1_REGISTER_15 |
0x0000153C screening type 1 register 15, same as screening_type_1_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_0 |
0x00001540 Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities, extending the capabilities into vendor specific protocols.
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_1 |
0x00001544 screening type 2 register 1, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_2 |
0x00001548 screening type 2 register 2, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_3 |
0x0000154C screening type 2 register 3, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_4 |
0x00001550 screening type 2 register 4, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_5 |
0x00001554 screening type 2 register 5, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_6 |
0x00001558 screening type 2 register 6, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_7 |
0x0000155C screening type 2 register 7, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_8 |
0x00001560 screening type 2 register 8, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_9 |
0x00001564 screening type 2 register 9, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_10 |
0x00001568 screening type 2 register 10, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_11 |
0x0000156C screening type 2 register 11, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_12 |
0x00001570 screening type 2 register 12, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_13 |
0x00001574 screening type 2 register 13, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_14 |
0x00001578 screening type 2 register 14, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_REGISTER_15 |
0x0000157C screening type 2 register 15, same as screening_type_2_register_0
| __IOM uint32_t ETH_Type::TX_SCHED_CTRL |
0x00001580 This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority
| __IM uint32_t ETH_Type::RESERVED19[3] |
| __IOM uint32_t ETH_Type::BW_RATE_LIMIT_Q0TO3 |
0x00001590 This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3.
| __IOM uint32_t ETH_Type::BW_RATE_LIMIT_Q4TO7 |
0x00001594 Not presents. EMAC has only 3 queues. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::BW_RATE_LIMIT_Q8TO11 |
0x00001598 Not presents. EMAC has only 3 queues. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::BW_RATE_LIMIT_Q12TO15 |
0x0000159C Not presents. EMAC has only 3 queues. Access to the register returns AHB error.
| __IOM uint32_t ETH_Type::TX_Q_SEG_ALLOC_Q0TO7 |
0x000015A0 This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file.
| __IM uint32_t ETH_Type::TX_Q_SEG_ALLOC_Q8TO15 |
0x000015A4 Not presents. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED20[6] |
| __IM uint32_t ETH_Type::RECEIVE_Q8_PTR |
0x000015C0 receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED21[6] |
| __IM uint32_t ETH_Type::RECEIVE_Q15_PTR |
0x000015DC Not presents.
| __IM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q8 |
0x000015E0 dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED22[6] |
| __IM uint32_t ETH_Type::DMA_RXBUF_SIZE_Q15 |
0x000015FC Not presents.
| __OM uint32_t ETH_Type::INT_Q1_ENABLE |
0x00001600 At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
| __OM uint32_t ETH_Type::INT_Q2_ENABLE |
0x00001604 At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
| __IM uint32_t ETH_Type::INT_Q3_ENABLE |
0x00001608 int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED23[3] |
| __IM uint32_t ETH_Type::INT_Q7_ENABLE |
0x00001618 Not presents.
| __IM uint32_t ETH_Type::RESERVED24 |
| __OM uint32_t ETH_Type::INT_Q1_DISABLE |
0x00001620 Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
| __OM uint32_t ETH_Type::INT_Q2_DISABLE |
0x00001624 Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
| __IM uint32_t ETH_Type::INT_Q3_DISABLE |
0x00001628 int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED25[3] |
| __IM uint32_t ETH_Type::INT_Q7_DISABLE |
0x00001638 Not presents.
| __IM uint32_t ETH_Type::RESERVED26 |
| __IM uint32_t ETH_Type::INT_Q1_MASK |
0x00001640 The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
| __IM uint32_t ETH_Type::INT_Q2_MASK |
0x00001644 The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
| __IM uint32_t ETH_Type::INT_Q3_MASK |
0x00001648 int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED27[3] |
| __IM uint32_t ETH_Type::INT_Q7_MASK |
0x00001658 Not presents.
| __IM uint32_t ETH_Type::RESERVED28 |
| __IM uint32_t ETH_Type::INT_Q8_ENABLE |
0x00001660 int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED29[6] |
| __IM uint32_t ETH_Type::INT_Q15_ENABLE |
0x0000167C Not presents.
| __IM uint32_t ETH_Type::INT_Q8_DISABLE |
0x00001680 int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED30[6] |
| __IM uint32_t ETH_Type::INT_Q15_DISABLE |
0x0000169C Not presents.
| __IM uint32_t ETH_Type::INT_Q8_MASK |
0x000016A0 int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error.
| __IM uint32_t ETH_Type::RESERVED31[6] |
| __IM uint32_t ETH_Type::INT_Q15_MASK |
0x000016BC Not presents.
| __IM uint32_t ETH_Type::RESERVED32[8] |
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_0 |
0x000016E0 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_1 |
0x000016E4 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_2 |
0x000016E8 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_3 |
0x000016EC Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_4 |
0x000016F0 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_5 |
0x000016F4 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_6 |
0x000016F8 Ethertype Register
| __IOM uint32_t ETH_Type::SCREENING_TYPE_2_ETHERTYPE_REG_7 |
0x000016FC Ethertype Register
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_0_WORD_0 |
0x00001700 'Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7 to 0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15 to 8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. '
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_0_WORD_1 |
0x00001704 'Type2 Compare Word 1'
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_1_WORD_0 |
0x00001708 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_1_WORD_1 |
0x0000170C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_2_WORD_0 |
0x00001710 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_2_WORD_1 |
0x00001714 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_3_WORD_0 |
0x00001718 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_3_WORD_1 |
0x0000171C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_4_WORD_0 |
0x00001720 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_4_WORD_1 |
0x00001724 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_5_WORD_0 |
0x00001728 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_5_WORD_1 |
0x0000172C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_6_WORD_0 |
0x00001730 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_6_WORD_1 |
0x00001734 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_7_WORD_0 |
0x00001738 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_7_WORD_1 |
0x0000173C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_8_WORD_0 |
0x00001740 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_8_WORD_1 |
0x00001744 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_9_WORD_0 |
0x00001748 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_9_WORD_1 |
0x0000174C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_10_WORD_0 |
0x00001750 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_10_WORD_1 |
0x00001754 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_11_WORD_0 |
0x00001758 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_11_WORD_1 |
0x0000175C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_12_WORD_0 |
0x00001760 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_12_WORD_1 |
0x00001764 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_13_WORD_0 |
0x00001768 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_13_WORD_1 |
0x0000176C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_14_WORD_0 |
0x00001770 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_14_WORD_1 |
0x00001774 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_15_WORD_0 |
0x00001778 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_15_WORD_1 |
0x0000177C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_16_WORD_0 |
0x00001780 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_16_WORD_1 |
0x00001784 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_17_WORD_0 |
0x00001788 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_17_WORD_1 |
0x0000178C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_18_WORD_0 |
0x00001790 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_18_WORD_1 |
0x00001794 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_19_WORD_0 |
0x00001798 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_19_WORD_1 |
0x0000179C same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_20_WORD_0 |
0x000017A0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_20_WORD_1 |
0x000017A4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_21_WORD_0 |
0x000017A8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_21_WORD_1 |
0x000017AC same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_22_WORD_0 |
0x000017B0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_22_WORD_1 |
0x000017B4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_23_WORD_0 |
0x000017B8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_23_WORD_1 |
0x000017BC same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_24_WORD_0 |
0x000017C0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_24_WORD_1 |
0x000017C4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_25_WORD_0 |
0x000017C8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_25_WORD_1 |
0x000017CC same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_26_WORD_0 |
0x000017D0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_26_WORD_1 |
0x000017D4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_27_WORD_0 |
0x000017D8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_27_WORD_1 |
0x000017DC same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_28_WORD_0 |
0x000017E0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_28_WORD_1 |
0x000017E4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_29_WORD_0 |
0x000017E8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_29_WORD_1 |
0x000017EC same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_30_WORD_0 |
0x000017F0 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_30_WORD_1 |
0x000017F4 same as type2_compare_0_word_1
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_31_WORD_0 |
0x000017F8 same as type2_compare_0_word_0
| __IOM uint32_t ETH_Type::TYPE2_COMPARE_31_WORD_1 |
0x000017FC same as type2_compare_0_word_1