General Description

This section describes the Macroses defined by the UBM for FRU Overview Area options.

Macros
#define	MTB_UBM_FRU_OA_2WIRE_ARRANGEMENT_NO_MUX (0x00U)
	No mux present.

#define	MTB_UBM_FRU_OA_2WIRE_ARRANGEMENT_DFC_MUX (0x01U)
	DFC 2Wire interface behind Mux.

#define	MTB_UBM_FRU_OA_2WIRE_ARRANGEMENT_DFC_CONTROLLER_MUX (0x03U)
	UBM Controller(s) and DFC 2Wire interface located behind Mux.

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_NO_LIMIT (0x00U)
	2Wire Maximum byte count More...

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_16BYTES (0x01U)
	16 bytes

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_32BYTES (0x02U)
	32 bytes

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_64BYTES (0x03U)
	64 bytes

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_128BYTES (0x04U)
	128 bytes

#define	MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_256BYTES (0x05U)
	256 bytes

#define	MTB_UBM_FRU_OA_F_PERST_NO_OVERRIDE (0x00U)
	DFC PERST# Management Override. More...

#define	MTB_UBM_FRU_OA_F_PERST_MANAGED_UPON_INSTALL (0x40U)
	DFC PERST# Managed upon install.

#define	MTB_UBM_FRU_OA_F_PERST_AUTO_UPON_INSTALL (0x80U)
	DFC PERST# Automatically released upon install.

#define	MTB_UBM_FRU_OA_F_OSCM_NO_INC (0x00U)
	Operation State Count Mask insrement feature. More...

#define	MTB_UBM_FRU_OA_F_OSCM_INC (0x20U)
	Operational State transitions cause the Change Count field to increment.

#define	MTB_UBM_FRU_OA_F_DTICC_NO_INC (0x00U)
	Drive Type Installed Change Count Mask Increment feature. More...

#define	MTB_UBM_FRU_OA_F_DTICC_INC (0x10U)
	Drive Type Installed field changes cause the Change Count field to increment.

#define	MTB_UBM_FRU_OA_F_PCIE_RES_NO_INC (0x00U)
	PCIe Reset Change Count Mask Increment feature. More...

#define	MTB_UBM_FRU_OA_F_PCIE_RES_INC (0x08U)
	PCIe Reset field changes cause the Change Count field to increment.

#define	MTB_UBM_FRU_OA_F_CHANGE_DETECT (0x00U)
	CPRSNT Legacy Mode - the behavior of the CPRSNT/CHANGE_DETECT# signal. More...

#define	MTB_UBM_FRU_OA_F_CPRSNT (0x04U)
	CPRSNT# legacy operation.

#define	MTB_UBM_FRU_OA_F_WR_NO_CHECKS_CHECK (0x00U)
	Write Checksum Checking feature. More...

#define	MTB_UBM_FRU_OA_F_WR_CHECKS_CHECK (0x02U)
	Checksum checking is enabled.

#define	MTB_UBM_FRU_OA_F_RD_NO_CHECKS_CHECK (0x00U)
	Read Checksum Creation feature. More...

#define	MTB_UBM_FRU_OA_F_RD_CHECKS_CREATION (0x01U)
	Checksum Creation is enabled.

#define	MTB_UBM_FRU_OA_F_SMBRST_NOP (0x00U)
	DFC SMBRST signal for all DFCs. More...

#define	MTB_UBM_FRU_OA_F_SMBRST_INIT_SEQ (0x100U)
	Initiate DFC SMBus Reset sequence.

#define	MTB_UBM_FRU_OA_2W_MUX_CH_ENABLE_LOC (0x00U)
	2Wire Mux Enable Channel Selection Method More...

#define	MTB_UBM_FRU_OA_2W_MUX_CH_ENABLE_LOC_CB (0x01U)
	Channels are selected using enable bit and channel byte.

#define	MTB_UBM_FRU_OA_2W_MUX_ENABLE_NA (0x00U)
	2Wire Mux Enable Bit Location More...

#define	MTB_UBM_FRU_OA_2W_MUX_ENABLE_2CH_SEL (0x02U)
	Mux Enable located at Bit 2 of Channel Select Byte.

#define	MTB_UBM_FRU_OA_2W_MUX_ENABLE_3CH_SEL (0x03U)
	Mux Enable located at Bit 3 of Channel Select Byte.

#define	MTB_UBM_FRU_OA_2W_MUX_NO_MUX (0x00U)
	2Wire Mux Channel Count More...

#define	MTB_UBM_FRU_OA_2W_MUX_2CH (0x01U)
	2 Channel Mux implemented

#define	MTB_UBM_FRU_OA_2W_MUX_4CH (0x02U)
	4 Channel Mux implemented

#define	MTB_UBM_FRU_OA_2W_MUX_8CH (0x03U)
	8 Channel Mux implemented

Macro Definition Documentation

◆ MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_NO_LIMIT

#define MTB_UBM_FRU_OA_2WIRE_MUX_BYTE_CNT_NO_LIMIT (0x00U)

2Wire Maximum byte count

No Limit

◆ MTB_UBM_FRU_OA_F_PERST_NO_OVERRIDE

#define MTB_UBM_FRU_OA_F_PERST_NO_OVERRIDE (0x00U)

DFC PERST# Management Override.

No override

◆ MTB_UBM_FRU_OA_F_OSCM_NO_INC

#define MTB_UBM_FRU_OA_F_OSCM_NO_INC (0x00U)

Operation State Count Mask insrement feature.

Operational State transitions do not cause the Change Count field to increment

◆ MTB_UBM_FRU_OA_F_DTICC_NO_INC

#define MTB_UBM_FRU_OA_F_DTICC_NO_INC (0x00U)

Drive Type Installed Change Count Mask Increment feature.

Drive Type Installed field changes do not cause the Change Count field to increment

◆ MTB_UBM_FRU_OA_F_PCIE_RES_NO_INC

#define MTB_UBM_FRU_OA_F_PCIE_RES_NO_INC (0x00U)

PCIe Reset Change Count Mask Increment feature.

PCIe Reset field changes do not cause the Change Count field to increment

◆ MTB_UBM_FRU_OA_F_CHANGE_DETECT

#define MTB_UBM_FRU_OA_F_CHANGE_DETECT (0x00U)

CPRSNT Legacy Mode - the behavior of the CPRSNT/CHANGE_DETECT# signal.

CHANGE_DETECT# interrupt operation

◆ MTB_UBM_FRU_OA_F_WR_NO_CHECKS_CHECK

#define MTB_UBM_FRU_OA_F_WR_NO_CHECKS_CHECK (0x00U)

Write Checksum Checking feature.

No Checksum Checking

◆ MTB_UBM_FRU_OA_F_RD_NO_CHECKS_CHECK

#define MTB_UBM_FRU_OA_F_RD_NO_CHECKS_CHECK (0x00U)

Read Checksum Creation feature.

No Checksum Creation is performed

◆ MTB_UBM_FRU_OA_F_SMBRST_NOP

#define MTB_UBM_FRU_OA_F_SMBRST_NOP (0x00U)

DFC SMBRST signal for all DFCs.

NOP (e.g. No DFC SMBus Reset sequence outstanding)

◆ MTB_UBM_FRU_OA_2W_MUX_CH_ENABLE_LOC

#define MTB_UBM_FRU_OA_2W_MUX_CH_ENABLE_LOC (0x00U)

2Wire Mux Enable Channel Selection Method

Channels are selected using bit location

◆ MTB_UBM_FRU_OA_2W_MUX_ENABLE_NA

#define MTB_UBM_FRU_OA_2W_MUX_ENABLE_NA (0x00U)

2Wire Mux Enable Bit Location

Mux Enable is not applicable

◆ MTB_UBM_FRU_OA_2W_MUX_NO_MUX

#define MTB_UBM_FRU_OA_2W_MUX_NO_MUX (0x00U)

2Wire Mux Channel Count

No Mux implemented