General Description

Basic set of APIs for interacting with the XENSIV(TM) BGT60TRxx 60GHz FMCW radar sensors.

The library allows:

sensor initialization
set/get individual registers of the sensor
start/stop the frame generation
read the digitized IF signal from the sensor FIFO
set the FIFO level-filling threshold
enable/disable the data test mode
software reset the sensor

More information about the XENSIV(TM) BGT60TRxx 60GHz FMCW radar sensors is available at: https://www.infineon.com/cms/de/product/sensor/radar-sensors/radar-sensors-for-iot/60ghz-radar/

Data Structures
struct	xensiv_bgt60trxx_t
	XENSIV(TM) BGT60TRxx sensor device object. More...

Macros
#define	XENSIV_BGT60TRXX_STATUS_OK (0)
	Result code indicating successful operation. More...

#define	XENSIV_BGT60TRXX_STATUS_COM_ERROR (1)
	Result code indicating a communication error. More...

#define	XENSIV_BGT60TRXX_STATUS_DEV_ERROR (2)
	Result code indicating an unsupported device error. More...

#define	XENSIV_BGT60TRXX_STATUS_TIMEOUT_ERROR (3)
	Result code indicating an operation timeout error. More...

#define	XENSIV_BGT60TRXX_STATUS_GSR0_ERROR (4)
	Result code indicating that an error occurred while reading from FIFO. More...

#define	XENSIV_BGT60TRXX_INITIAL_TEST_WORD (0x0001U)
	Initial value of the LFSR test sequence generator. More...

#define	XENSIV_BGT60TRXX_NUM_SAMPLES_FIFO_WORD (2U)
	Number of samples stored in a FIFO word (24 bits). More...

#define	XENSIV_BGT60TRXX_FIFO_WORD_SIZE_BYTES (3U) /* two ADC samples of 12bits */
	Size of the radar device FIFO word in bytes. More...

#define	XENSIV_BGT60TRXX_SPI_BURST_HEADER_SIZE_BYTES (4U)
	Size of the header in the SPI burst transfer. More...

#define	XENSIV_BGT60TRXX_RESET_WAIT_TIMEOUT (0xFFFFFFFFU)
	Timeout for wait on software reset done. More...

#define	XENSIV_BGT60TRXX_REG_MAIN (0x00U)

#define	XENSIV_BGT60TRXX_REG_ADC0 (0x01U)

#define	XENSIV_BGT60TRXX_REG_CHIP_ID (0x02U)

#define	XENSIV_BGT60TRXX_REG_STAT1 (0x03U)

#define	XENSIV_BGT60TRXX_REG_PACR1 (0x04U)

#define	XENSIV_BGT60TRXX_REG_PACR2 (0x05U)

#define	XENSIV_BGT60TRXX_REG_SFCTL (0x06U)

#define	XENSIV_BGT60TRXX_REG_SADC_CTRL (0x07U)

#define	XENSIV_BGT60TRXX_REG_CSI_0 (0x08U)

#define	XENSIV_BGT60TRXX_REG_CSI_1 (0x09U)

#define	XENSIV_BGT60TRXX_REG_CSI_2 (0x0aU)

#define	XENSIV_BGT60TRXX_REG_CSCI (0x0bU)

#define	XENSIV_BGT60TRXX_REG_CSDS_0 (0x0cU)

#define	XENSIV_BGT60TRXX_REG_CSDS_1 (0x0dU)

#define	XENSIV_BGT60TRXX_REG_CSDS_2 (0x0eU)

#define	XENSIV_BGT60TRXX_REG_CSCDS (0x0fU)

#define	XENSIV_BGT60TRXX_REG_CSU1_0 (0x10U)

#define	XENSIV_BGT60TRXX_REG_CSU1_1 (0x11U)

#define	XENSIV_BGT60TRXX_REG_CSU1_2 (0x12U)

#define	XENSIV_BGT60TRXX_REG_CSD1_0 (0x13U)

#define	XENSIV_BGT60TRXX_REG_CSD1_1 (0x14U)

#define	XENSIV_BGT60TRXX_REG_CSD1_2 (0x15U)

#define	XENSIV_BGT60TRXX_REG_CSC1 (0x16U)

#define	XENSIV_BGT60TRXX_REG_CSU2_0 (0x17U)

#define	XENSIV_BGT60TRXX_REG_CSU2_1 (0x18U)

#define	XENSIV_BGT60TRXX_REG_CSU2_2 (0x19U)

#define	XENSIV_BGT60TRXX_REG_CSD2_0 (0x1aU)

#define	XENSIV_BGT60TRXX_REG_CSD2_1 (0x1bU)

#define	XENSIV_BGT60TRXX_REG_CSD2_2 (0x1cU)

#define	XENSIV_BGT60TRXX_REG_CSC2 (0x1dU)

#define	XENSIV_BGT60TRXX_REG_CSU3_0 (0x1eU)

#define	XENSIV_BGT60TRXX_REG_CSU3_1 (0x1fU)

#define	XENSIV_BGT60TRXX_REG_CSU3_2 (0x20U)

#define	XENSIV_BGT60TRXX_REG_CSD3_0 (0x21U)

#define	XENSIV_BGT60TRXX_REG_CSD3_1 (0x22U)

#define	XENSIV_BGT60TRXX_REG_CSD3_2 (0x23U)

#define	XENSIV_BGT60TRXX_REG_CSC3 (0x24U)

#define	XENSIV_BGT60TRXX_REG_CSU4_0 (0x25U)

#define	XENSIV_BGT60TRXX_REG_CSU4_1 (0x26U)

#define	XENSIV_BGT60TRXX_REG_CSU4_2 (0x27U)

#define	XENSIV_BGT60TRXX_REG_CSD4_0 (0x28U)

#define	XENSIV_BGT60TRXX_REG_CSD4_1 (0x29U)

#define	XENSIV_BGT60TRXX_REG_CSD4_2 (0x2aU)

#define	XENSIV_BGT60TRXX_REG_CSC4 (0x2bU)

#define	XENSIV_BGT60TRXX_REG_CCR0 (0x2cU)

#define	XENSIV_BGT60TRXX_REG_CCR1 (0x2dU)

#define	XENSIV_BGT60TRXX_REG_CCR2 (0x2eU)

#define	XENSIV_BGT60TRXX_REG_CCR3 (0x2fU)

#define	XENSIV_BGT60TRXX_REG_PLL1_0 (0x30U)

#define	XENSIV_BGT60TRXX_REG_PLL1_1 (0x31U)

#define	XENSIV_BGT60TRXX_REG_PLL1_2 (0x32U)

#define	XENSIV_BGT60TRXX_REG_PLL1_3 (0x33U)

#define	XENSIV_BGT60TRXX_REG_PLL1_4 (0x34U)

#define	XENSIV_BGT60TRXX_REG_PLL1_5 (0x35U)

#define	XENSIV_BGT60TRXX_REG_PLL1_6 (0x36U)

#define	XENSIV_BGT60TRXX_REG_PLL1_7 (0x37U)

#define	XENSIV_BGT60TRXX_REG_PLL2_0 (0x38U)

#define	XENSIV_BGT60TRXX_REG_PLL2_1 (0x39U)

#define	XENSIV_BGT60TRXX_REG_PLL2_2 (0x3aU)

#define	XENSIV_BGT60TRXX_REG_PLL2_3 (0x3bU)

#define	XENSIV_BGT60TRXX_REG_PLL2_4 (0x3cU)

#define	XENSIV_BGT60TRXX_REG_PLL2_5 (0x3dU)

#define	XENSIV_BGT60TRXX_REG_PLL2_6 (0x3eU)

#define	XENSIV_BGT60TRXX_REG_PLL2_7 (0x3fU)

#define	XENSIV_BGT60TRXX_REG_PLL3_0 (0x40U)

#define	XENSIV_BGT60TRXX_REG_PLL3_1 (0x41U)

#define	XENSIV_BGT60TRXX_REG_PLL3_2 (0x42U)

#define	XENSIV_BGT60TRXX_REG_PLL3_3 (0x43U)

#define	XENSIV_BGT60TRXX_REG_PLL3_4 (0x44U)

#define	XENSIV_BGT60TRXX_REG_PLL3_5 (0x45U)

#define	XENSIV_BGT60TRXX_REG_PLL3_6 (0x46U)

#define	XENSIV_BGT60TRXX_REG_PLL3_7 (0x47U)

#define	XENSIV_BGT60TRXX_REG_PLL4_0 (0x48U)

#define	XENSIV_BGT60TRXX_REG_PLL4_1 (0x49U)

#define	XENSIV_BGT60TRXX_REG_PLL4_2 (0x4aU)

#define	XENSIV_BGT60TRXX_REG_PLL4_3 (0x4bU)

#define	XENSIV_BGT60TRXX_REG_PLL4_4 (0x4cU)

#define	XENSIV_BGT60TRXX_REG_PLL4_5 (0x4dU)

#define	XENSIV_BGT60TRXX_REG_PLL4_6 (0x4eU)

#define	XENSIV_BGT60TRXX_REG_PLL4_7 (0x4fU)

#define	XENSIV_BGT60TRXX_REG_RFT0 (0x55U)

#define	XENSIV_BGT60TRXX_REG_RFT1 (0x56U)

#define	XENSIV_BGT60TRXX_REG_PLL_DFT0 (0x59U)

#define	XENSIV_BGT60TRXX_REG_STAT0 (0x5dU)

#define	XENSIV_BGT60TRXX_REG_SDAC_RESULT (0x5eU)

#define	XENSIV_BGT60TRXX_REG_FSTAT_TR13C (0x5fU)

#define	XENSIV_BGT60TRXX_REG_FIFO_TR13C (0x60U)

#define	XENSIV_BGT60TRXX_REG_FSTAT_UTR13D (0x5fU)

#define	XENSIV_BGT60TRXX_REG_FIFO_UTR13D (0x63U)

#define	XENSIV_BGT60TRXX_REG_FSTAT_UTR11 (0x63U)

#define	XENSIV_BGT60TRXX_REG_FIFO_UTR11 (0x64U)

#define	XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_POS (0)

#define	XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_MSK (0x000001UL)

#define	XENSIV_BGT60TRXX_REG_MAIN_RESET_POS (1)

#define	XENSIV_BGT60TRXX_REG_MAIN_RESET_MSK (0x00000eUL)

#define	XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_POS (0)

#define	XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_MSK (0x0000ffUL)

#define	XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_POS (8)

#define	XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_MSK (0xffff00UL)

#define	XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_POS (0)

#define	XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_MSK (0x000fffUL)

#define	XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_POS (12)

#define	XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_MSK (0xfff000UL)

#define	XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_POS (0)

#define	XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_MSK (0x001fffUL)

#define	XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_POS (13)

#define	XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_MSK (0x002000UL)

#define	XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_POS (16)

#define	XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_MSK (0x010000UL)

#define	XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_POS (17)

#define	XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_MSK (0x020000UL)

#define	XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_POS (18)

#define	XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_MSK (0x040000UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_POS (0)

#define	XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_MSK (0x000001UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_POS (1)

#define	XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_MSK (0x000002UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_POS (2)

#define	XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_MSK (0x000004UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_POS (3)

#define	XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_MSK (0x000008UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_PM_POS (5)

#define	XENSIV_BGT60TRXX_REG_STAT0_PM_MSK (0x0000e0UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_POS (8)

#define	XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_MSK (0x000700UL)

#define	XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_POS (11)

#define	XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_MSK (0x003800UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_POS (0)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_MSK (0x003fffUL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_POS (17)

#define	XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_MSK (0x020000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_POS (18)

#define	XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_MSK (0x040000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_POS (19)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_MSK (0x080000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_POS (20)

#define	XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_MSK (0x100000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_CREF_POS (21)

#define	XENSIV_BGT60TRXX_REG_FSTAT_CREF_MSK (0x200000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FULL_POS (22)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FULL_MSK (0x400000UL)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_POS (23)

#define	XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_MSK (0x800000UL)

#define	XENSIV_BGT60TRXX_REG_GSR0_FOU_ERR_MSK (0x01UL)

#define	XENSIV_BGT60TRXX_REG_GSR0_MISO_HS_READ_MSK (0x02UL)

#define	XENSIV_BGT60TRXX_REG_GSR0_SPI_BURST_ERR_MSK (0x04UL)

#define	XENSIV_BGT60TRXX_REG_GSR0_CLK_NUM_ERR_MSK (0x08UL)

Enumerations
enum	xensiv_bgt60trxx_reset_t { XENSIV_BGT60TRXX_RESET_SW = 0x1 << XENSIV_BGT60TRXX_REG_MAIN_RESET_POS, XENSIV_BGT60TRXX_RESET_FSM = 0x2 << XENSIV_BGT60TRXX_REG_MAIN_RESET_POS, XENSIV_BGT60TRXX_RESET_FIFO = 0x4 << XENSIV_BGT60TRXX_REG_MAIN_RESET_POS }
	enum defining the different reset commands passed to xensiv_bgt60trxx_soft_reset() More...

enum	xensiv_bgt60trxx_device_t { XENSIV_DEVICE_BGT60TR13C = 0, XENSIV_DEVICE_BGT60UTR13D = 1, XENSIV_DEVICE_BGT60UTR11 = 2, XENSIV_DEVICE_UNKNOWN = -1 }
	enum with supported devices More...

Functions
int32_t	xensiv_bgt60trxx_init (xensiv_bgt60trxx_t dev, void iface, bool high_speed)
	Initializes the XENSIV(TM) BGT60TRxx radar sensor device. More...

xensiv_bgt60trxx_device_t	xensiv_bgt60trxx_get_device (const xensiv_bgt60trxx_t *dev)
	Obtains the detected sensor device name. More...

int32_t	xensiv_bgt60trxx_config (xensiv_bgt60trxx_t dev, const uint32_t regs, uint32_t len)
	Configures the XENSIV(TM) BGT60TRxx radar sensor device. More...

int32_t	xensiv_bgt60trxx_set_reg (const xensiv_bgt60trxx_t *dev, uint32_t reg_addr, uint32_t data)
	Writes the given data buffer into the sensor device. More...

int32_t	xensiv_bgt60trxx_get_reg (const xensiv_bgt60trxx_t dev, uint32_t reg_addr, uint32_t data)
	Reads from the sensor device into the given data buffer. More...

uint16_t	xensiv_bgt60trxx_get_fifo_size (const xensiv_bgt60trxx_t *dev)
	Obtains the sensor device FIFO size. More...

int32_t	xensiv_bgt60trxx_get_fifo_status (const xensiv_bgt60trxx_t dev, uint32_t status)
	Obtains the sensor device FIFO status. More...

int32_t	xensiv_bgt60trxx_set_fifo_limit (const xensiv_bgt60trxx_t *dev, uint32_t num_samples)
	Sets the FIFO compare reference value. More...

int32_t	xensiv_bgt60trxx_get_fifo_data (const xensiv_bgt60trxx_t dev, uint16_t data, uint32_t num_samples)
	Reads from the sensor device FIFO into the given data buffer. More...

int32_t	xensiv_bgt60trxx_start_frame (const xensiv_bgt60trxx_t *dev, bool start)
	Starts/stops radar frame generation. More...

int32_t	xensiv_bgt60trxx_soft_reset (const xensiv_bgt60trxx_t *dev, xensiv_bgt60trxx_reset_t reset_type)
	Triggers a soft reset of the sensor device. More...

int32_t	xensiv_bgt60trxx_enable_data_test_mode (const xensiv_bgt60trxx_t *dev, bool enable)
	Enables/disables generation of a test sequence out of FIFO. More...

void	xensiv_bgt60trxx_hard_reset (const xensiv_bgt60trxx_t *dev)
	Performs a hard reset of the sensor device. More...

uint16_t	xensiv_bgt60trxx_get_next_test_word (uint16_t cur_test_word)
	Utility function that generates test sequence data that can be used to compare against the FIFO data obtained from device sensor when data test mode is enabled. More...

Data Structure Documentation

◆ xensiv_bgt60trxx_t

struct xensiv_bgt60trxx_t

Data Fields
void *	iface	Pointer to platform-specific SPI interface object provided to the xensiv_bgt60trxx_platform_spi_transfer function.
const struct xensiv_bgt60trxx_type *	type	Device type detected during initialization.
bool	high_speed	SPI speed mode.

Macro Definition Documentation

◆ XENSIV_BGT60TRXX_STATUS_OK

#define XENSIV_BGT60TRXX_STATUS_OK (0)

Result code indicating successful operation.

◆ XENSIV_BGT60TRXX_STATUS_COM_ERROR

#define XENSIV_BGT60TRXX_STATUS_COM_ERROR (1)

Result code indicating a communication error.

◆ XENSIV_BGT60TRXX_STATUS_DEV_ERROR

#define XENSIV_BGT60TRXX_STATUS_DEV_ERROR (2)

Result code indicating an unsupported device error.

◆ XENSIV_BGT60TRXX_STATUS_TIMEOUT_ERROR

#define XENSIV_BGT60TRXX_STATUS_TIMEOUT_ERROR (3)

Result code indicating an operation timeout error.

◆ XENSIV_BGT60TRXX_STATUS_GSR0_ERROR

#define XENSIV_BGT60TRXX_STATUS_GSR0_ERROR (4)

Result code indicating that an error occurred while reading from FIFO.

◆ XENSIV_BGT60TRXX_INITIAL_TEST_WORD

#define XENSIV_BGT60TRXX_INITIAL_TEST_WORD (0x0001U)

Initial value of the LFSR test sequence generator.

◆ XENSIV_BGT60TRXX_NUM_SAMPLES_FIFO_WORD

#define XENSIV_BGT60TRXX_NUM_SAMPLES_FIFO_WORD (2U)

Number of samples stored in a FIFO word (24 bits).

◆ XENSIV_BGT60TRXX_FIFO_WORD_SIZE_BYTES

#define XENSIV_BGT60TRXX_FIFO_WORD_SIZE_BYTES (3U) /* two ADC samples of 12bits */

Size of the radar device FIFO word in bytes.

◆ XENSIV_BGT60TRXX_SPI_BURST_HEADER_SIZE_BYTES

#define XENSIV_BGT60TRXX_SPI_BURST_HEADER_SIZE_BYTES (4U)

Size of the header in the SPI burst transfer.

◆ XENSIV_BGT60TRXX_RESET_WAIT_TIMEOUT

#define XENSIV_BGT60TRXX_RESET_WAIT_TIMEOUT (0xFFFFFFFFU)

Timeout for wait on software reset done.

◆ XENSIV_BGT60TRXX_REG_MAIN

#define XENSIV_BGT60TRXX_REG_MAIN (0x00U)

MAIN: addr

◆ XENSIV_BGT60TRXX_REG_ADC0

#define XENSIV_BGT60TRXX_REG_ADC0 (0x01U)

ADC0: addr

◆ XENSIV_BGT60TRXX_REG_CHIP_ID

#define XENSIV_BGT60TRXX_REG_CHIP_ID (0x02U)

CHIP_ID: addr

◆ XENSIV_BGT60TRXX_REG_STAT1

#define XENSIV_BGT60TRXX_REG_STAT1 (0x03U)

STAT1: addr

◆ XENSIV_BGT60TRXX_REG_PACR1

#define XENSIV_BGT60TRXX_REG_PACR1 (0x04U)

PACR1: addr

◆ XENSIV_BGT60TRXX_REG_PACR2

#define XENSIV_BGT60TRXX_REG_PACR2 (0x05U)

PACR2: addr

◆ XENSIV_BGT60TRXX_REG_SFCTL

#define XENSIV_BGT60TRXX_REG_SFCTL (0x06U)

SFCTL: addr

◆ XENSIV_BGT60TRXX_REG_SADC_CTRL

#define XENSIV_BGT60TRXX_REG_SADC_CTRL (0x07U)

SADC_CTRL: addr

◆ XENSIV_BGT60TRXX_REG_CSI_0

#define XENSIV_BGT60TRXX_REG_CSI_0 (0x08U)

CSI_0: addr

◆ XENSIV_BGT60TRXX_REG_CSI_1

#define XENSIV_BGT60TRXX_REG_CSI_1 (0x09U)

CSI_1: addr

◆ XENSIV_BGT60TRXX_REG_CSI_2

#define XENSIV_BGT60TRXX_REG_CSI_2 (0x0aU)

CSI_2: addr

◆ XENSIV_BGT60TRXX_REG_CSCI

#define XENSIV_BGT60TRXX_REG_CSCI (0x0bU)

CSCI: addr

◆ XENSIV_BGT60TRXX_REG_CSDS_0

#define XENSIV_BGT60TRXX_REG_CSDS_0 (0x0cU)

CSDS_0: addr

◆ XENSIV_BGT60TRXX_REG_CSDS_1

#define XENSIV_BGT60TRXX_REG_CSDS_1 (0x0dU)

CSDS_1: addr

◆ XENSIV_BGT60TRXX_REG_CSDS_2

#define XENSIV_BGT60TRXX_REG_CSDS_2 (0x0eU)

REG_CSDS_2: addr

◆ XENSIV_BGT60TRXX_REG_CSCDS

#define XENSIV_BGT60TRXX_REG_CSCDS (0x0fU)

REG_CSCDS: addr

◆ XENSIV_BGT60TRXX_REG_CSU1_0

#define XENSIV_BGT60TRXX_REG_CSU1_0 (0x10U)

REG_CS1_U_0: addr

◆ XENSIV_BGT60TRXX_REG_CSU1_1

#define XENSIV_BGT60TRXX_REG_CSU1_1 (0x11U)

REG_CS1_U_1: addr

◆ XENSIV_BGT60TRXX_REG_CSU1_2

#define XENSIV_BGT60TRXX_REG_CSU1_2 (0x12U)

REG_CS1_U_2: addr

◆ XENSIV_BGT60TRXX_REG_CSD1_0

#define XENSIV_BGT60TRXX_REG_CSD1_0 (0x13U)

REG_CS1_D_0: addr

◆ XENSIV_BGT60TRXX_REG_CSD1_1

#define XENSIV_BGT60TRXX_REG_CSD1_1 (0x14U)

REG_CS1_D_1: addr

◆ XENSIV_BGT60TRXX_REG_CSD1_2

#define XENSIV_BGT60TRXX_REG_CSD1_2 (0x15U)

REG_CS1_D_2: addr

◆ XENSIV_BGT60TRXX_REG_CSC1

#define XENSIV_BGT60TRXX_REG_CSC1 (0x16U)

REG_CSC1: addr

◆ XENSIV_BGT60TRXX_REG_CSU2_0

#define XENSIV_BGT60TRXX_REG_CSU2_0 (0x17U)

REG_CS2_U_0: addr

◆ XENSIV_BGT60TRXX_REG_CSU2_1

#define XENSIV_BGT60TRXX_REG_CSU2_1 (0x18U)

REG_CS2_U_1: addr

◆ XENSIV_BGT60TRXX_REG_CSU2_2

#define XENSIV_BGT60TRXX_REG_CSU2_2 (0x19U)

REG_CS2_U_2: addr

◆ XENSIV_BGT60TRXX_REG_CSD2_0

#define XENSIV_BGT60TRXX_REG_CSD2_0 (0x1aU)

REG_CS2_D_0: addr

◆ XENSIV_BGT60TRXX_REG_CSD2_1

#define XENSIV_BGT60TRXX_REG_CSD2_1 (0x1bU)

REG_CS2_D_1: addr

◆ XENSIV_BGT60TRXX_REG_CSD2_2

#define XENSIV_BGT60TRXX_REG_CSD2_2 (0x1cU)

REG_CS2_D_2: addr

◆ XENSIV_BGT60TRXX_REG_CSC2

#define XENSIV_BGT60TRXX_REG_CSC2 (0x1dU)

REG_CSC2: addr

◆ XENSIV_BGT60TRXX_REG_CSU3_0

#define XENSIV_BGT60TRXX_REG_CSU3_0 (0x1eU)

REG_CS3_U_0: addr

◆ XENSIV_BGT60TRXX_REG_CSU3_1

#define XENSIV_BGT60TRXX_REG_CSU3_1 (0x1fU)

REG_CS3_U_1: addr

◆ XENSIV_BGT60TRXX_REG_CSU3_2

#define XENSIV_BGT60TRXX_REG_CSU3_2 (0x20U)

REG_CS3_U_2: addr

◆ XENSIV_BGT60TRXX_REG_CSD3_0

#define XENSIV_BGT60TRXX_REG_CSD3_0 (0x21U)

REG_CS3_D_0: addr

◆ XENSIV_BGT60TRXX_REG_CSD3_1

#define XENSIV_BGT60TRXX_REG_CSD3_1 (0x22U)

REG_CS3_D_1: addr

◆ XENSIV_BGT60TRXX_REG_CSD3_2

#define XENSIV_BGT60TRXX_REG_CSD3_2 (0x23U)

REG_CS3_D_2: addr

◆ XENSIV_BGT60TRXX_REG_CSC3

#define XENSIV_BGT60TRXX_REG_CSC3 (0x24U)

REG_CSC3: addr

◆ XENSIV_BGT60TRXX_REG_CSU4_0

#define XENSIV_BGT60TRXX_REG_CSU4_0 (0x25U)

REG_CS4_U_0: addr

◆ XENSIV_BGT60TRXX_REG_CSU4_1

#define XENSIV_BGT60TRXX_REG_CSU4_1 (0x26U)

REG_CS4_U_1: addr

◆ XENSIV_BGT60TRXX_REG_CSU4_2

#define XENSIV_BGT60TRXX_REG_CSU4_2 (0x27U)

REG_CS4_U_2: addr

◆ XENSIV_BGT60TRXX_REG_CSD4_0

#define XENSIV_BGT60TRXX_REG_CSD4_0 (0x28U)

REG_CS4_D_0: addr

◆ XENSIV_BGT60TRXX_REG_CSD4_1

#define XENSIV_BGT60TRXX_REG_CSD4_1 (0x29U)

REG_CS4_D_1: addr

◆ XENSIV_BGT60TRXX_REG_CSD4_2

#define XENSIV_BGT60TRXX_REG_CSD4_2 (0x2aU)

REG_CS4_D_2: addr

◆ XENSIV_BGT60TRXX_REG_CSC4

#define XENSIV_BGT60TRXX_REG_CSC4 (0x2bU)

REG_CSC4: addr

◆ XENSIV_BGT60TRXX_REG_CCR0

#define XENSIV_BGT60TRXX_REG_CCR0 (0x2cU)

REG_CCR0: addr

◆ XENSIV_BGT60TRXX_REG_CCR1

#define XENSIV_BGT60TRXX_REG_CCR1 (0x2dU)

REG_CCR1: addr

◆ XENSIV_BGT60TRXX_REG_CCR2

#define XENSIV_BGT60TRXX_REG_CCR2 (0x2eU)

REG_CCR2: addr

◆ XENSIV_BGT60TRXX_REG_CCR3

#define XENSIV_BGT60TRXX_REG_CCR3 (0x2fU)

REG_CCR3: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_0

#define XENSIV_BGT60TRXX_REG_PLL1_0 (0x30U)

REG_PLL1_0: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_1

#define XENSIV_BGT60TRXX_REG_PLL1_1 (0x31U)

REG_PLL1_1: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_2

#define XENSIV_BGT60TRXX_REG_PLL1_2 (0x32U)

REG_PLL1_2: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_3

#define XENSIV_BGT60TRXX_REG_PLL1_3 (0x33U)

REG_PLL1_3: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_4

#define XENSIV_BGT60TRXX_REG_PLL1_4 (0x34U)

REG_PLL1_4: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_5

#define XENSIV_BGT60TRXX_REG_PLL1_5 (0x35U)

REG_PLL1_5: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_6

#define XENSIV_BGT60TRXX_REG_PLL1_6 (0x36U)

REG_PLL1_6: addr

◆ XENSIV_BGT60TRXX_REG_PLL1_7

#define XENSIV_BGT60TRXX_REG_PLL1_7 (0x37U)

REG_PLL1_7: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_0

#define XENSIV_BGT60TRXX_REG_PLL2_0 (0x38U)

REG_PLL2_0: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_1

#define XENSIV_BGT60TRXX_REG_PLL2_1 (0x39U)

REG_PLL2_1: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_2

#define XENSIV_BGT60TRXX_REG_PLL2_2 (0x3aU)

REG_PLL2_2: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_3

#define XENSIV_BGT60TRXX_REG_PLL2_3 (0x3bU)

REG_PLL2_3: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_4

#define XENSIV_BGT60TRXX_REG_PLL2_4 (0x3cU)

REG_PLL2_4: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_5

#define XENSIV_BGT60TRXX_REG_PLL2_5 (0x3dU)

REG_PLL2_5: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_6

#define XENSIV_BGT60TRXX_REG_PLL2_6 (0x3eU)

REG_PLL2_6: addr

◆ XENSIV_BGT60TRXX_REG_PLL2_7

#define XENSIV_BGT60TRXX_REG_PLL2_7 (0x3fU)

REG_PLL2_7: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_0

#define XENSIV_BGT60TRXX_REG_PLL3_0 (0x40U)

REG_PLL3_0: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_1

#define XENSIV_BGT60TRXX_REG_PLL3_1 (0x41U)

REG_PLL3_1: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_2

#define XENSIV_BGT60TRXX_REG_PLL3_2 (0x42U)

REG_PLL3_2: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_3

#define XENSIV_BGT60TRXX_REG_PLL3_3 (0x43U)

REG_PLL3_3: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_4

#define XENSIV_BGT60TRXX_REG_PLL3_4 (0x44U)

REG_PLL3_4: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_5

#define XENSIV_BGT60TRXX_REG_PLL3_5 (0x45U)

REG_PLL3_5: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_6

#define XENSIV_BGT60TRXX_REG_PLL3_6 (0x46U)

REG_PLL3_6: addr

◆ XENSIV_BGT60TRXX_REG_PLL3_7

#define XENSIV_BGT60TRXX_REG_PLL3_7 (0x47U)

REG_PLL3_7: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_0

#define XENSIV_BGT60TRXX_REG_PLL4_0 (0x48U)

REG_PLL4_0: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_1

#define XENSIV_BGT60TRXX_REG_PLL4_1 (0x49U)

REG_PLL4_1: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_2

#define XENSIV_BGT60TRXX_REG_PLL4_2 (0x4aU)

REG_PLL4_2: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_3

#define XENSIV_BGT60TRXX_REG_PLL4_3 (0x4bU)

REG_PLL4_3: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_4

#define XENSIV_BGT60TRXX_REG_PLL4_4 (0x4cU)

REG_PLL4_4: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_5

#define XENSIV_BGT60TRXX_REG_PLL4_5 (0x4dU)

REG_PLL4_5: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_6

#define XENSIV_BGT60TRXX_REG_PLL4_6 (0x4eU)

REG_PLL4_6: addr

◆ XENSIV_BGT60TRXX_REG_PLL4_7

#define XENSIV_BGT60TRXX_REG_PLL4_7 (0x4fU)

REG_PLL4_7: addr

◆ XENSIV_BGT60TRXX_REG_RFT0

#define XENSIV_BGT60TRXX_REG_RFT0 (0x55U)

REG_RFT0: addr

◆ XENSIV_BGT60TRXX_REG_RFT1

#define XENSIV_BGT60TRXX_REG_RFT1 (0x56U)

REG_RFT1: addr

◆ XENSIV_BGT60TRXX_REG_PLL_DFT0

#define XENSIV_BGT60TRXX_REG_PLL_DFT0 (0x59U)

REG_PDFT0: addr

◆ XENSIV_BGT60TRXX_REG_STAT0

#define XENSIV_BGT60TRXX_REG_STAT0 (0x5dU)

REG_STAT0: addr

◆ XENSIV_BGT60TRXX_REG_SDAC_RESULT

#define XENSIV_BGT60TRXX_REG_SDAC_RESULT (0x5eU)

REG_SADC_RESULT: addr

◆ XENSIV_BGT60TRXX_REG_FSTAT_TR13C

#define XENSIV_BGT60TRXX_REG_FSTAT_TR13C (0x5fU)

TR13C REG_FSTAT: addr

◆ XENSIV_BGT60TRXX_REG_FIFO_TR13C

#define XENSIV_BGT60TRXX_REG_FIFO_TR13C (0x60U)

TR13C REG_FIFO: addr

◆ XENSIV_BGT60TRXX_REG_FSTAT_UTR13D

#define XENSIV_BGT60TRXX_REG_FSTAT_UTR13D (0x5fU)

UTR13D REG_FSTAT: addr

◆ XENSIV_BGT60TRXX_REG_FIFO_UTR13D

#define XENSIV_BGT60TRXX_REG_FIFO_UTR13D (0x63U)

UTR13D REG_FIFO: addr

◆ XENSIV_BGT60TRXX_REG_FSTAT_UTR11

#define XENSIV_BGT60TRXX_REG_FSTAT_UTR11 (0x63U)

UTR11 REG_FSTAT: addr

◆ XENSIV_BGT60TRXX_REG_FIFO_UTR11

#define XENSIV_BGT60TRXX_REG_FIFO_UTR11 (0x64U)

UTR11: REG_FIFO: addr

◆ XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_POS

#define XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_POS (0)

FRAME_START: pos

◆ XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_MSK

#define XENSIV_BGT60TRXX_REG_MAIN_FRAME_START_MSK (0x000001UL)

FRAME_START: msk

◆ XENSIV_BGT60TRXX_REG_MAIN_RESET_POS

#define XENSIV_BGT60TRXX_REG_MAIN_RESET_POS (1)

RESET: pos

◆ XENSIV_BGT60TRXX_REG_MAIN_RESET_MSK

#define XENSIV_BGT60TRXX_REG_MAIN_RESET_MSK (0x00000eUL)

RESET: msk

◆ XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_POS

#define XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_POS (0)

RF_ID: pos

◆ XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_MSK

#define XENSIV_BGT60TRXX_REG_CHIP_ID_RF_ID_MSK (0x0000ffUL)

RF_ID: msk

◆ XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_POS

#define XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_POS (8)

DIGITAL_ID: pos

◆ XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_MSK

#define XENSIV_BGT60TRXX_REG_CHIP_ID_DIGITAL_ID_MSK (0xffff00UL)

DIGITAL_ID: msk

◆ XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_POS

#define XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_POS (0)

SHAPE_GRP_CNT: pos

◆ XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_MSK

#define XENSIV_BGT60TRXX_REG_STAT1_SHAPE_GRP_CNT_MSK (0x000fffUL)

SHAPE_GRP_CNT: msk

◆ XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_POS

#define XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_POS (12)

FRAME_CNT: pos

◆ XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_MSK

#define XENSIV_BGT60TRXX_REG_STAT1_FRAME_CNT_MSK (0xfff000UL)

FRAME_CNT: msk

◆ XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_POS

#define XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_POS (0)

FIFO_CREF: pos

◆ XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_MSK

#define XENSIV_BGT60TRXX_REG_SFCTL_FIFO_CREF_MSK (0x001fffUL)

FIFO_CREF: msk

◆ XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_POS

#define XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_POS (13)

FIFO_LP_MODE: pos

◆ XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_MSK

#define XENSIV_BGT60TRXX_REG_SFCTL_FIFO_LP_MODE_MSK (0x002000UL)

FIFO_LP_MODE: msk

◆ XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_POS

#define XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_POS (16)

MISO_HF_READ: pos

◆ XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_MSK

#define XENSIV_BGT60TRXX_REG_SFCTL_MISO_HS_READ_MSK (0x010000UL)

MISO_HF_READ: msk

◆ XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_POS

#define XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_POS (17)

LFSR_EN: pos

◆ XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_MSK

#define XENSIV_BGT60TRXX_REG_SFCTL_LFSR_EN_MSK (0x020000UL)

LFSR_EN: msk

◆ XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_POS

#define XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_POS (18)

PREFIX_EN: pos

◆ XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_MSK

#define XENSIV_BGT60TRXX_REG_SFCTL_PREFIX_EN_MSK (0x040000UL)

PREFIX_EN: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_POS

#define XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_POS (0)

SADC_RDY: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_SADC_RDY_MSK (0x000001UL)

SADC_RDY: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_POS

#define XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_POS (1)

MADC_RDY: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_MADC_RDY_MSK (0x000002UL)

MADC_RDY: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_POS

#define XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_POS (2)

MADC_BGUP: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_MADC_BGUP_MSK (0x000004UL)

MADC_BGUP: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_POS

#define XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_POS (3)

LDO_RDY: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_LDO_RDY_MSK (0x000008UL)

LDO_RDY: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_PM_POS

#define XENSIV_BGT60TRXX_REG_STAT0_PM_POS (5)

PM: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_PM_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_PM_MSK (0x0000e0UL)

PM: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_POS

#define XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_POS (8)

CH_IDX: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_CH_IDX_MSK (0x000700UL)

CH_IDX: msk

◆ XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_POS

#define XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_POS (11)

SH_IDX: pos

◆ XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_MSK

#define XENSIV_BGT60TRXX_REG_STAT0_SH_IDX_MSK (0x003800UL)

SH_IDX: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_POS (0)

FILL_STATUS: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_FILL_STATUS_MSK (0x003fffUL)

FILL_STATUS: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_POS (17)

CLK_NUM_ERR: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_CLK_NUM_ERR_MSK (0x020000UL)

CLK_NUM_ERR: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_POS (18)

SPI_BURST_ERR: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_SPI_BURST_ERR_MSK (0x040000UL)

SPI_BURST_ERR: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_POS (19)

FUF_ERR: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_FUF_ERR_MSK (0x080000UL)

FUF_ERR: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_POS (20)

EMPTY: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_EMPTY_MSK (0x100000UL)

EMPTY: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_CREF_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_CREF_POS (21)

CREF: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_CREF_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_CREF_MSK (0x200000UL)

CREF: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_FULL_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_FULL_POS (22)

FULL: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_FULL_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_FULL_MSK (0x400000UL)

FULL: msk

◆ XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_POS

#define XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_POS (23)

FOF_ERR: pos

◆ XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_MSK

#define XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_MSK (0x800000UL)

FOF_ERR: msk

◆ XENSIV_BGT60TRXX_REG_GSR0_FOU_ERR_MSK

#define XENSIV_BGT60TRXX_REG_GSR0_FOU_ERR_MSK (0x01UL)

FOU_ERR: msk

◆ XENSIV_BGT60TRXX_REG_GSR0_MISO_HS_READ_MSK

#define XENSIV_BGT60TRXX_REG_GSR0_MISO_HS_READ_MSK (0x02UL)

MISO_HS_READ: msk

◆ XENSIV_BGT60TRXX_REG_GSR0_SPI_BURST_ERR_MSK

#define XENSIV_BGT60TRXX_REG_GSR0_SPI_BURST_ERR_MSK (0x04UL)

SPI_BURST_ERR: msk

◆ XENSIV_BGT60TRXX_REG_GSR0_CLK_NUM_ERR_MSK

#define XENSIV_BGT60TRXX_REG_GSR0_CLK_NUM_ERR_MSK (0x08UL)

CLK_NUM_ERR: msk

Enumeration Type Documentation

◆ xensiv_bgt60trxx_reset_t

enum xensiv_bgt60trxx_reset_t

enum defining the different reset commands passed to xensiv_bgt60trxx_soft_reset()

Enumerator
XENSIV_BGT60TRXX_RESET_SW	Software reset. Resets all registers to default state. Resets all internal counters (e.g. shape, frame). Perform FIFO reset. Perform FSM reset
XENSIV_BGT60TRXX_RESET_FSM	FSM reset. Resets FSM to deep sleep mode. Resets FSM internal counters for channel/shape set and timers
XENSIV_BGT60TRXX_RESET_FIFO	FIFO reset. Reset the read and write pointers of the FIFO. Perform an implicit FSM reset

◆ xensiv_bgt60trxx_device_t

enum xensiv_bgt60trxx_device_t

enum with supported devices

Enumerator
XENSIV_DEVICE_BGT60TR13C	BGT60TR13C.
XENSIV_DEVICE_BGT60UTR13D	BGT60UTR13D.
XENSIV_DEVICE_BGT60UTR11	BGT60UTR11.
XENSIV_DEVICE_UNKNOWN	Unknown not supported device.

Function Documentation

◆ xensiv_bgt60trxx_init()

int32_t xensiv_bgt60trxx_init	(	xensiv_bgt60trxx_t *	dev,
		void *	iface,
		bool	high_speed
	)

Initializes the XENSIV(TM) BGT60TRxx radar sensor device.

It checks the integrity of the serial communication interface. Detects and identify the connected radar sensor.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object. The caller must allocate the memory for this object but the init function will initialize its contents.
[in]	iface	Pointer to the interface object used to communicate with the sensor over SPI. Typically, a pointer to the platform-specific SPI interface object.
[in]	high_speed	The XENSIV(TM) BGT60TRxx sensor offers an additional high speed mode which increase the timing budget on SPI master side by sending out data via DO with the rising edge instead of the falling edge of the CLK.

Returns: XENSIV_BGT60TRXX_STATUS_OK if the initialization was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_get_device()

xensiv_bgt60trxx_device_t xensiv_bgt60trxx_get_device ( const xensiv_bgt60trxx_t * dev )

Obtains the detected sensor device name.

Parameters

[in] dev Pointer to the XENSIV(TM) BGT60TRxx sensor device object.

Returns: sensor device name.

◆ xensiv_bgt60trxx_config()

int32_t xensiv_bgt60trxx_config	(	xensiv_bgt60trxx_t *	dev,
		const uint32_t *	regs,
		uint32_t	len
	)

Configures the XENSIV(TM) BGT60TRxx radar sensor device.

It performs a SW reset and applies the sensor configurator given in the regs array The register configuration can be generated using the BGT60TRxx configurator tool.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	regs	Pointer to the configuration registers list.
[in]	len	Length of the configuration registers list.

Returns: XENSIV_BGT60TRXX_STATUS_OK if the initialization was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_set_reg()

int32_t xensiv_bgt60trxx_set_reg	(	const xensiv_bgt60trxx_t *	dev,
		uint32_t	reg_addr,
		uint32_t	data
	)

Writes the given data buffer into the sensor device.

Writes the given data buffer to the sensor register map starting at the register address.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	reg_addr	Register address.
[in]	data	Data to be written in the sensor register.

Returns: XENSIV_BGT60TRXX_STATUS_OK if writing to the sensor register wash successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_get_reg()

int32_t xensiv_bgt60trxx_get_reg	(	const xensiv_bgt60trxx_t *	dev,
		uint32_t	reg_addr,
		uint32_t *	data
	)

Reads from the sensor device into the given data buffer.

Reads from the sensor register map sensor starting at register address into the given data buffer.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	reg_addr	Register address.
[out]	data	Data to be written in the sensor register.

Returns: XENSIV_BGT60TRXX_STATUS_OK if reading from the sensor register was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_get_fifo_size()

uint16_t xensiv_bgt60trxx_get_fifo_size ( const xensiv_bgt60trxx_t * dev )

Obtains the sensor device FIFO size.

Parameters

[in] dev Pointer to the XENSIV(TM) BGT60TRxx sensor device object.

Returns: FIFO size.

◆ xensiv_bgt60trxx_get_fifo_status()

int32_t xensiv_bgt60trxx_get_fifo_status	(	const xensiv_bgt60trxx_t *	dev,
		uint32_t *	status
	)

Obtains the sensor device FIFO status.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[out]	status	Pointer to populate with FIFO status. The status value is used to get fifo error information when compared with bit masks from xensiv_bgt60trxx_regs.h i.e. to check for fifo overflow error use XENSIV_BGT60TRXX_REG_FSTAT_FOF_ERR_MSK & status

Returns: XENSIV_BGT60TRXX_STATUS_OK if reading the FIFO status was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_set_fifo_limit()

int32_t xensiv_bgt60trxx_set_fifo_limit	(	const xensiv_bgt60trxx_t *	dev,
		uint32_t	num_samples
	)

Sets the FIFO compare reference value.

The beat signal signal is sampled, digitized, and stored into the sensor FIFO. When the filling level is greater than the FIFO compare reference (CREF), an interrupt is issued, indicating to the controlling processor the availability of at least CREF samples in the FIFO.

Parameters

[in,out]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	num_samples	Number of samples stored in FIFO to trigger interrupt.

Note: Should be an even number

Returns: XENSIV_BGT60TRXX_STATUS_OK if setting the new FIFO limit was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_get_fifo_data()

int32_t xensiv_bgt60trxx_get_fifo_data	(	const xensiv_bgt60trxx_t *	dev,
		uint16_t *	data,
		uint32_t	num_samples
	)

Reads from the sensor device FIFO into the given data buffer.

The beat signal is sampled, digitized, and stored into the sensor FIFO. This function reads out the sensor FIFO contents and places it in the given buffer.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[out]	data	Pointer to a data buffer.
[in]	num_samples	Number of samples to read from the sensor.

Returns: XENSIV_BGT60TRXX_STATUS_OK if reading from the FIFO was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_start_frame()

int32_t xensiv_bgt60trxx_start_frame	(	const xensiv_bgt60trxx_t *	dev,
		bool	start
	)

Starts/stops radar frame generation.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	start	Starts/stops control of frames.

Returns: XENSIV_BGT60TRXX_STATUS_OK if the starting the frame generation was successful, else an error indicating what went wrong.

◆ xensiv_bgt60trxx_soft_reset()

int32_t xensiv_bgt60trxx_soft_reset	(	const xensiv_bgt60trxx_t *	dev,
		xensiv_bgt60trxx_reset_t	reset_type
	)

Triggers a soft reset of the sensor device.

Triggers reset and waits for reset done.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	reset_type	Reset type, combination of .

Returns: XENSIV_BGT60TRXX_STATUS_OK if the soft reset was successful, XENSIV_BGT60TRXX_STATUS_TIMEOUT_ERROR if a timeout occurs while waiting reset to finish; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_enable_data_test_mode()

int32_t xensiv_bgt60trxx_enable_data_test_mode	(	const xensiv_bgt60trxx_t *	dev,
		bool	enable
	)

Enables/disables generation of a test sequence out of FIFO.

Enables/disables the output of test sequence data instead of the ADC data for the first ADC channel. This can be used to check data from the radar sensor FIFO against a defined bit sequence.

Note: ADC Channel 1 need to be enabled in the BGT60TRxx configuration.

Parameters

[in]	dev	Pointer to the XENSIV(TM) BGT60TRxx sensor device object.
[in]	enable	Enable/disable the output of the test sequence data.

Returns: XENSIV_BGT60TRXX_STATUS_OK if enabling the data testomode was successful; else an error indicating what went wrong.

◆ xensiv_bgt60trxx_hard_reset()

void xensiv_bgt60trxx_hard_reset ( const xensiv_bgt60trxx_t * dev )

Performs a hard reset of the sensor device.

Parameters

[in] dev Pointer to the XENSIV(TM) BGT60TRxx sensor device object.

◆ xensiv_bgt60trxx_get_next_test_word()

uint16_t xensiv_bgt60trxx_get_next_test_word ( uint16_t cur_test_word )

Utility function that generates test sequence data that can be used to compare against the FIFO data obtained from device sensor when data test mode is enabled.

Implements the LFSR sequence generator based on the polynomial x^12+x^11+x^10+x^4+1. Argument variable cur_test_word keeps the current state of the LFSR generator and should be initialized using XENSIV_BGT60TRXX_INITIAL_TEST_WORD.

uint16_t test_word = XENSIV_BGT60TRXX_INITIAL_TEST_WORD;

test_word = xensiv_bgt60trxx_get_next_test_word(test_word);

Parameters

[in] cur_test_word Keeps the current state of the LFSR generator.

Returns: Next word in the LFSR sequence.

General Description

Data Structures

Macros

Enumerations

Functions

Data Structure Documentation

◆ xensiv_bgt60trxx_t

Macro Definition Documentation

◆ XENSIV_BGT60TRXX_STATUS_OK

◆ XENSIV_BGT60TRXX_STATUS_COM_ERROR

◆ XENSIV_BGT60TRXX_STATUS_DEV_ERROR

◆ XENSIV_BGT60TRXX_STATUS_TIMEOUT_ERROR

◆ XENSIV_BGT60TRXX_STATUS_GSR0_ERROR

◆ XENSIV_BGT60TRXX_INITIAL_TEST_WORD

◆ XENSIV_BGT60TRXX_NUM_SAMPLES_FIFO_WORD

◆ XENSIV_BGT60TRXX_FIFO_WORD_SIZE_BYTES

◆ XENSIV_BGT60TRXX_SPI_BURST_HEADER_SIZE_BYTES

◆ XENSIV_BGT60TRXX_RESET_WAIT_TIMEOUT

◆ XENSIV_BGT60TRXX_REG_MAIN

◆ XENSIV_BGT60TRXX_REG_ADC0

◆ XENSIV_BGT60TRXX_REG_CHIP_ID

◆ XENSIV_BGT60TRXX_REG_STAT1

◆ XENSIV_BGT60TRXX_REG_PACR1

◆ XENSIV_BGT60TRXX_REG_PACR2

◆ XENSIV_BGT60TRXX_REG_SFCTL

◆ XENSIV_BGT60TRXX_REG_SADC_CTRL

◆ XENSIV_BGT60TRXX_REG_CSI_0

◆ XENSIV_BGT60TRXX_REG_CSI_1

◆ XENSIV_BGT60TRXX_REG_CSI_2

◆ XENSIV_BGT60TRXX_REG_CSCI

◆ XENSIV_BGT60TRXX_REG_CSDS_0

◆ XENSIV_BGT60TRXX_REG_CSDS_1

◆ XENSIV_BGT60TRXX_REG_CSDS_2

◆ XENSIV_BGT60TRXX_REG_CSCDS

◆ XENSIV_BGT60TRXX_REG_CSU1_0

◆ XENSIV_BGT60TRXX_REG_CSU1_1

◆ XENSIV_BGT60TRXX_REG_CSU1_2

◆ XENSIV_BGT60TRXX_REG_CSD1_0

◆ XENSIV_BGT60TRXX_REG_CSD1_1

◆ XENSIV_BGT60TRXX_REG_CSD1_2

◆ XENSIV_BGT60TRXX_REG_CSC1

◆ XENSIV_BGT60TRXX_REG_CSU2_0

◆ XENSIV_BGT60TRXX_REG_CSU2_1

◆ XENSIV_BGT60TRXX_REG_CSU2_2

◆ XENSIV_BGT60TRXX_REG_CSD2_0

◆ XENSIV_BGT60TRXX_REG_CSD2_1

◆ XENSIV_BGT60TRXX_REG_CSD2_2

◆ XENSIV_BGT60TRXX_REG_CSC2

◆ XENSIV_BGT60TRXX_REG_CSU3_0

◆ XENSIV_BGT60TRXX_REG_CSU3_1

◆ XENSIV_BGT60TRXX_REG_CSU3_2

◆ XENSIV_BGT60TRXX_REG_CSD3_0

◆ XENSIV_BGT60TRXX_REG_CSD3_1

◆ XENSIV_BGT60TRXX_REG_CSD3_2

◆ XENSIV_BGT60TRXX_REG_CSC3

◆ XENSIV_BGT60TRXX_REG_CSU4_0

◆ XENSIV_BGT60TRXX_REG_CSU4_1

◆ XENSIV_BGT60TRXX_REG_CSU4_2

◆ XENSIV_BGT60TRXX_REG_CSD4_0

◆ XENSIV_BGT60TRXX_REG_CSD4_1

◆ XENSIV_BGT60TRXX_REG_CSD4_2

◆ XENSIV_BGT60TRXX_REG_CSC4

◆ XENSIV_BGT60TRXX_REG_CCR0

◆ XENSIV_BGT60TRXX_REG_CCR1

◆ XENSIV_BGT60TRXX_REG_CCR2

◆ XENSIV_BGT60TRXX_REG_CCR3

◆ XENSIV_BGT60TRXX_REG_PLL1_0

◆ XENSIV_BGT60TRXX_REG_PLL1_1

◆ XENSIV_BGT60TRXX_REG_PLL1_2

◆ XENSIV_BGT60TRXX_REG_PLL1_3

◆ XENSIV_BGT60TRXX_REG_PLL1_4

◆ XENSIV_BGT60TRXX_REG_PLL1_5

◆ XENSIV_BGT60TRXX_REG_PLL1_6

◆ XENSIV_BGT60TRXX_REG_PLL1_7

◆ XENSIV_BGT60TRXX_REG_PLL2_0

◆ XENSIV_BGT60TRXX_REG_PLL2_1

◆ XENSIV_BGT60TRXX_REG_PLL2_2

◆ XENSIV_BGT60TRXX_REG_PLL2_3

◆ XENSIV_BGT60TRXX_REG_PLL2_4

◆ XENSIV_BGT60TRXX_REG_PLL2_5