The Medium Frequency Domain Clock is present only in SRSS_ver1_3.
Consists of MFO - the Medium Frequency Oscillator, and CLK_MF - the Medium Frequency Clock divider. This clock chain is designed to source the LCD block in Deep Sleep mode, see cy_en_seglcd_lsclk_t.
◆ Cy_SysClk_MfoEnable()
__STATIC_INLINE void Cy_SysClk_MfoEnable |
( |
bool |
deepSleepEnable | ) |
|
Enables the MFO.
- Parameters
-
deepSleepEnable | enables MFO operation is Deep Sleep low power mode. |
- Function Usage
◆ Cy_SysClk_MfoIsEnabled()
__STATIC_INLINE bool Cy_SysClk_MfoIsEnabled |
( |
void |
| ) |
|
Reports whether MFO is enabled or not.
- Returns
- false - disabled
true - enabled
- Function Usage
◆ Cy_SysClk_MfoDisable()
__STATIC_INLINE void Cy_SysClk_MfoDisable |
( |
void |
| ) |
|
Disables the MFO.
- Function Usage
◆ Cy_SysClk_ClkMfEnable()
__STATIC_INLINE void Cy_SysClk_ClkMfEnable |
( |
void |
| ) |
|
Enables the CLK_MF.
- Function Usage
◆ Cy_SysClk_ClkMfIsEnabled()
__STATIC_INLINE bool Cy_SysClk_ClkMfIsEnabled |
( |
void |
| ) |
|
Reports whether CLK_MF is enabled or not.
- Returns
- false - disabled
true - enabled
- Function Usage
◆ Cy_SysClk_ClkMfDisable()
__STATIC_INLINE void Cy_SysClk_ClkMfDisable |
( |
void |
| ) |
|
Disables the CLK_MF.
- Function Usage
◆ Cy_SysClk_ClkMfSetDivider()
__STATIC_INLINE void Cy_SysClk_ClkMfSetDivider |
( |
uint32_t |
divider | ) |
|
Sets the clock divider for CLK_MF.
- Precondition
- If the CLK_MF is already enabled - it should be disabled prior to use this function by Cy_SysClk_ClkMfDisable.
- Parameters
-
divider | divider value between 1 and 256. |
- Function Usage
◆ Cy_SysClk_ClkMfGetDivider()
__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetDivider |
( |
void |
| ) |
|
Returns the clock divider of CLK_MF.
- Returns
- divider value in range 1..256.
- Function Usage
◆ Cy_SysClk_ClkMfGetFrequency()
__STATIC_INLINE uint32_t Cy_SysClk_ClkMfGetFrequency |
( |
void |
| ) |
|
Reports the output clock signal frequency of CLK_MF.
- Returns
- The frequency, in Hz.
- Function Usage