PSoC 6 Peripheral Driver Library

General Description

Functions

__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider (uint8_t divider)
 Sets the clock divider for the slow clock. More...
 
__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider (void)
 Reports the divider value for the slow clock. More...
 
__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency (void)
 Reports the frequency of the slow clock. More...
 

Function Documentation

◆ Cy_SysClk_ClkSlowSetDivider()

__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider ( uint8_t  divider)

Sets the clock divider for the slow clock.

The source of this clock is the peripheral clock (clkPeri), which is sourced from clkHf[0].

Parameters
dividerDivider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.
Note
Call SystemCoreClockUpdate after this function calling.
Function Usage
/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
CM0+ core must run at a frequency that is 1/32 of HFCLK0. */
/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
{
}
/* Get the CM0+ clock source frequency */
uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

◆ Cy_SysClk_ClkSlowGetDivider()

__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider ( void  )

Reports the divider value for the slow clock.

Returns
The divider value. The integer division done is by (divider value + 1), or division by 1 to 256.
Function Usage
/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
CM0+ core must run at a frequency that is 1/32 of HFCLK0. */
/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
{
}
/* Get the CM0+ clock source frequency */
uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

◆ Cy_SysClk_ClkSlowGetFrequency()

__STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency ( void  )

Reports the frequency of the slow clock.

Returns
The frequency, in Hz.
Function Usage
/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
CM0+ core must run at a frequency that is 1/32 of HFCLK0. */
/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
{
}
/* Get the CM0+ clock source frequency */
uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();