General Description

Functions
__STATIC_INLINE void	Cy_SysClk_ClkFastSetDivider (uint8_t divider)
	Sets the clock divider for the fast clock, which sources the main processor. More...

__STATIC_INLINE uint8_t	Cy_SysClk_ClkFastGetDivider (void)
	Returns the clock divider for the fast clock. More...

__STATIC_INLINE uint32_t	Cy_SysClk_ClkFastGetFrequency (void)
	Reports the frequency of the fast clock. More...

Function Documentation

__STATIC_INLINE void Cy_SysClk_ClkFastSetDivider ( uint8_t divider )

Sets the clock divider for the fast clock, which sources the main processor.

The source of this divider is clkHf[0].

Parameters

divider divider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.

Note: Call SystemCoreClockUpdate after this function calling.; Call Cy_SysLib_SetWaitStates before calling this function if CLK_FAST frequency is increasing.; Call Cy_SysLib_SetWaitStates after calling this function if CLK_FAST frequency is decreasing.

Function Usage: /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
CM4 core must run at a frequency that is 1/16 of HFCLK0. */
if(16u != Cy_SysClk_ClkFastGetDivider())
{
Cy_SysClk_ClkFastSetDivider(16u);
}
/* Get the CM4 clock source frequency */
uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();

__STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider ( void )

Returns the clock divider for the fast clock.

Returns: The divider value for the fast clock. The integer division done is by (divider value + 1), or division by 1 to 256.

Function Usage: /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
CM4 core must run at a frequency that is 1/16 of HFCLK0. */
if(16u != Cy_SysClk_ClkFastGetDivider())
{
Cy_SysClk_ClkFastSetDivider(16u);
}
/* Get the CM4 clock source frequency */
uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();

__STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency ( void )

Reports the frequency of the fast clock.

Function Usage: /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
CM4 core must run at a frequency that is 1/16 of HFCLK0. */
if(16u != Cy_SysClk_ClkFastGetDivider())
{
Cy_SysClk_ClkFastSetDivider(16u);
}
/* Get the CM4 clock source frequency */
uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();