SPI Transfer Status

General Description

Macros to check current SPI transfer status returned by Cy_SCB_SPI_GetTransferStatus function.

Each SPI transfer status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.

Macros
#define	CY_SCB_SPI_TRANSFER_ACTIVE   (0x01UL)
	Transfer operation started by Cy_SCB_SPI_Transfer is in progress.
#define	CY_SCB_SPI_TRANSFER_IN_FIFO   (0x02UL)
	All data elements specified by Cy_SCB_SPI_Transfer for transmission have been loaded into the TX FIFO.
#define	CY_SCB_SPI_SLAVE_TRANSFER_ERR   (SCB_INTR_S_SPI_BUS_ERROR_Msk)
	The slave was deselected at the wrong time. More...
#define	CY_SCB_SPI_TRANSFER_OVERFLOW   (SCB_INTR_RX_OVERFLOW_Msk)
	RX FIFO was full and there was an attempt to write to it. More...
#define	CY_SCB_SPI_TRANSFER_UNDERFLOW   (SCB_INTR_TX_UNDERFLOW_Msk)
	Applicable only for the slave mode. More...

Macro Definition Documentation

CY_SCB_SPI_SLAVE_TRANSFER_ERR

#define CY_SCB_SPI_SLAVE_TRANSFER_ERR   (SCB_INTR_S_SPI_BUS_ERROR_Msk)

The slave was deselected at the wrong time.

CY_SCB_SPI_TRANSFER_OVERFLOW

#define CY_SCB_SPI_TRANSFER_OVERFLOW   (SCB_INTR_RX_OVERFLOW_Msk)

RX FIFO was full and there was an attempt to write to it.

This additional data was dropped.

CY_SCB_SPI_TRANSFER_UNDERFLOW

#define CY_SCB_SPI_TRANSFER_UNDERFLOW   (SCB_INTR_TX_UNDERFLOW_Msk)

Applicable only for the slave mode.

The master tried to read more data elements than available in the TX FIFO.