General Description

Macros to check current EZI2C activity slave status returned by Cy_SCB_EZI2C_GetActivity function.

Each EZI2C slave status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.

Macros
#define	CY_SCB_EZI2C_STATUS_READ1 (0x01UL)
	The Read transfer intended for the primary slave address is complete. More...

#define	CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL)
	The Write transfer intended for the primary slave address is complete. More...

#define	CY_SCB_EZI2C_STATUS_READ2 (0x04UL)
	The Read transfer intended for the secondary slave address is complete. More...

#define	CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL)
	The Write transfer intended for the secondary slave address is complete. More...

#define	CY_SCB_EZI2C_STATUS_BUSY (0x10UL)
	A transfer intended for the primary address or secondary address is in progress. More...

#define	CY_SCB_EZI2C_STATUS_ERR (0x20UL)
	An error occurred during a transfer intended for the primary or secondary slave address. More...

Macro Definition Documentation

◆ CY_SCB_EZI2C_STATUS_READ1

#define CY_SCB_EZI2C_STATUS_READ1 (0x01UL)

The Read transfer intended for the primary slave address is complete.

The error condition status bit must be checked to ensure that the Read transfer was completed successfully.

◆ CY_SCB_EZI2C_STATUS_WRITE1

#define CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL)

The Write transfer intended for the primary slave address is complete.

The buffer content was modified. The error condition status bit must be checked to ensure that the Write transfer was completed successfully.

◆ CY_SCB_EZI2C_STATUS_READ2

#define CY_SCB_EZI2C_STATUS_READ2 (0x04UL)

The Read transfer intended for the secondary slave address is complete.

The error condition status bit must be checked to ensure that the Read transfer was completed successfully.

◆ CY_SCB_EZI2C_STATUS_WRITE2

#define CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL)

The Write transfer intended for the secondary slave address is complete.

The buffer content was modified. The error condition status bit must be checked to ensure that the Write transfer was completed successfully.

◆ CY_SCB_EZI2C_STATUS_BUSY

#define CY_SCB_EZI2C_STATUS_BUSY (0x10UL)

A transfer intended for the primary address or secondary address is in progress.

The status bit is set after an address match and cleared on a Stop or ReStart condition.

◆ CY_SCB_EZI2C_STATUS_ERR

#define CY_SCB_EZI2C_STATUS_ERR (0x20UL)

An error occurred during a transfer intended for the primary or secondary slave address.

The sources of the error are: a misplaced Start or Stop condition or lost arbitration while the slave drives SDA. When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an invalid byte. Discard the buffer content in this case.