Interrupt Masks

General Description

Macros
#define	CY_I2S_INTR_TX_TRIGGER   (I2S_INTR_TX_TRIGGER_Msk)
	Bit 0: Less entries in the TX FIFO than specified by Trigger Level. More...
#define	CY_I2S_INTR_TX_NOT_FULL   (I2S_INTR_TX_NOT_FULL_Msk)
	Bit 1: TX FIFO is not full. More...
#define	CY_I2S_INTR_TX_EMPTY   (I2S_INTR_TX_EMPTY_Msk)
	Bit 4: TX FIFO is empty, i.e. More...
#define	CY_I2S_INTR_TX_OVERFLOW   (I2S_INTR_TX_OVERFLOW_Msk)
	Bit 5: Attempt to write to a full TX FIFO. More...
#define	CY_I2S_INTR_TX_UNDERFLOW   (I2S_INTR_TX_UNDERFLOW_Msk)
	Bit 6: Attempt to read from an empty TX FIFO. More...
#define	CY_I2S_INTR_TX_WD   (I2S_INTR_TX_WD_Msk)
	Bit 8: Tx watchdog event occurs. More...
#define	CY_I2S_INTR_RX_TRIGGER   (I2S_INTR_RX_TRIGGER_Msk)
	Bit 16: More entries in the RX FIFO than specified by Trigger Level. More...
#define	CY_I2S_INTR_RX_NOT_EMPTY   (I2S_INTR_RX_NOT_EMPTY_Msk)
	Bit 18: RX FIFO is not empty. More...
#define	CY_I2S_INTR_RX_FULL   (I2S_INTR_RX_FULL_Msk)
	Bit 19: RX FIFO is full. More...
#define	CY_I2S_INTR_RX_OVERFLOW   (I2S_INTR_RX_OVERFLOW_Msk)
	Bit 21: Attempt to write to a full RX FIFO. More...
#define	CY_I2S_INTR_RX_UNDERFLOW   (I2S_INTR_RX_UNDERFLOW_Msk)
	Bit 22: Attempt to read from an empty RX FIFO. More...
#define	CY_I2S_INTR_RX_WD   (I2S_INTR_RX_WD_Msk)
	Bit 24: Rx watchdog event occurs. More...

Macro Definition Documentation

CY_I2S_INTR_TX_TRIGGER

#define CY_I2S_INTR_TX_TRIGGER   (I2S_INTR_TX_TRIGGER_Msk)

Bit 0: Less entries in the TX FIFO than specified by Trigger Level.

CY_I2S_INTR_TX_NOT_FULL

#define CY_I2S_INTR_TX_NOT_FULL   (I2S_INTR_TX_NOT_FULL_Msk)

Bit 1: TX FIFO is not full.

CY_I2S_INTR_TX_EMPTY

#define CY_I2S_INTR_TX_EMPTY   (I2S_INTR_TX_EMPTY_Msk)

Bit 4: TX FIFO is empty, i.e.

it has 0 entries.

CY_I2S_INTR_TX_OVERFLOW

#define CY_I2S_INTR_TX_OVERFLOW   (I2S_INTR_TX_OVERFLOW_Msk)

Bit 5: Attempt to write to a full TX FIFO.

CY_I2S_INTR_TX_UNDERFLOW

#define CY_I2S_INTR_TX_UNDERFLOW   (I2S_INTR_TX_UNDERFLOW_Msk)

Bit 6: Attempt to read from an empty TX FIFO.

This happens when the IP is ready to transfer data and TX_EMPTY is '1'.

CY_I2S_INTR_TX_WD

#define CY_I2S_INTR_TX_WD   (I2S_INTR_TX_WD_Msk)

Bit 8: Tx watchdog event occurs.

CY_I2S_INTR_RX_TRIGGER

#define CY_I2S_INTR_RX_TRIGGER   (I2S_INTR_RX_TRIGGER_Msk)

Bit 16: More entries in the RX FIFO than specified by Trigger Level.

CY_I2S_INTR_RX_NOT_EMPTY

#define CY_I2S_INTR_RX_NOT_EMPTY   (I2S_INTR_RX_NOT_EMPTY_Msk)

Bit 18: RX FIFO is not empty.

CY_I2S_INTR_RX_FULL

#define CY_I2S_INTR_RX_FULL   (I2S_INTR_RX_FULL_Msk)

Bit 19: RX FIFO is full.

CY_I2S_INTR_RX_OVERFLOW

#define CY_I2S_INTR_RX_OVERFLOW   (I2S_INTR_RX_OVERFLOW_Msk)

Bit 21: Attempt to write to a full RX FIFO.

CY_I2S_INTR_RX_UNDERFLOW

#define CY_I2S_INTR_RX_UNDERFLOW   (I2S_INTR_RX_UNDERFLOW_Msk)

Bit 22: Attempt to read from an empty RX FIFO.

CY_I2S_INTR_RX_WD

#define CY_I2S_INTR_RX_WD   (I2S_INTR_RX_WD_Msk)

Bit 24: Rx watchdog event occurs.