Data Structures
struct	XMC_USIC_CH_t

Macros
#define	USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk

#define	USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos

#define	USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk

#define	USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk

#define	USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk

#define	USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos

#define	USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk

#define	USIC_CH_DXCR_INSW_Msk USIC_CH_DX0CR_INSW_Msk

#define	USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos

#define	USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk

#define	USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos

#define	XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE)

#define	XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE)

#define	XMC_USIC0_CH1 ((XMC_USIC_CH_t *)USIC0_CH1_BASE)

#define	XMC_USIC1 ((XMC_USIC_t *)USIC1_BASE)

#define	XMC_USIC1_CH0 ((XMC_USIC_CH_t *)USIC1_CH0_BASE)

#define	XMC_USIC1_CH1 ((XMC_USIC_CH_t *)USIC1_CH1_BASE)

#define	XMC_USIC2 ((XMC_USIC_t *)USIC2_BASE)

#define	XMC_USIC2_CH0 ((XMC_USIC_CH_t *)USIC2_CH0_BASE)

#define	XMC_USIC2_CH1 ((XMC_USIC_CH_t *)USIC2_CH1_BASE)

Typedefs
typedef USIC_GLOBAL_TypeDef	XMC_USIC_t

Enumerations
enum	XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t

enum	XMC_USIC_CH_BRG_CLOCK_SOURCE_t

enum	XMC_USIC_CH_BRG_CTQSEL_t

enum	XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t

enum	XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t

enum	XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t

enum	XMC_USIC_CH_DATA_OUTPUT_MODE_t

enum	XMC_USIC_CH_EVENT_t

enum	XMC_USIC_CH_FIFO_SIZE_t

enum	XMC_USIC_CH_INPUT_COMBINATION_MODE_t

enum	XMC_USIC_CH_INPUT_SAMPLING_FREQ_t

enum	XMC_USIC_CH_INPUT_t

enum	XMC_USIC_CH_INTERRUPT_NODE_POINTER_t

enum	XMC_USIC_CH_KERNEL_MODE_t

enum	XMC_USIC_CH_OPERATING_MODE_t

enum	XMC_USIC_CH_PARITY_MODE_t

enum	XMC_USIC_CH_PASSIVE_DATA_LEVEL_t

enum	XMC_USIC_CH_RBUF_STATUS_t

enum	XMC_USIC_CH_RXFIFO_EVENT_CONF_t

enum	XMC_USIC_CH_RXFIFO_EVENT_t

enum	XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t

enum	XMC_USIC_CH_SHIFT_DIRECTION_t

enum	XMC_USIC_CH_START_TRANSMISION_MODE_t

enum	XMC_USIC_CH_STATUS_t

enum	XMC_USIC_CH_TBUF_STATUS_SET_t

enum	XMC_USIC_CH_TBUF_STATUS_t

enum	XMC_USIC_CH_TXFIFO_EVENT_CONF_t

enum	XMC_USIC_CH_TXFIFO_EVENT_t

enum	XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t

Functions
void	XMC_USIC_CH_ConfigExternalInputSignalToBRG (XMC_USIC_CH_t *const channel, const uint16_t pdiv, const uint32_t oversampling, const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)

void	XMC_USIC_CH_ConfigureShiftClockOutput (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)

void	XMC_USIC_CH_ConnectInputDataShiftToDataInput (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_ConnectInputDataShiftToPPP (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_Disable (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_DisableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_DisableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_DisableFrameLengthControl (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_DisableInputDigitalFilter (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_DisableInputInversion (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_DisableInputSync (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_DisableTBUFDataValidTrigger (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_DisableTimeMeasurement (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_DisableWordLengthControl (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_Enable (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_EnableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_EnableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_EnableFrameLengthControl (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_EnableInputDigitalFilter (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_EnableInputInversion (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_EnableInputSync (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)

void	XMC_USIC_CH_EnableTBUFDataValidTrigger (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_EnableTimeMeasurement (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_EnableWordLengthControl (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_GetBaudrate (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_GetCaptureTimerValue (const XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_GetMCLKFrequency (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_GetReceiveBufferStatus (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_GetSCLKFrequency (XMC_USIC_CH_t *const channel)

XMC_USIC_CH_TBUF_STATUS_t	XMC_USIC_CH_GetTransmitBufferStatus (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_InvalidateReadData (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_RXFIFO_ClearEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_RXFIFO_Configure (XMC_USIC_CH_t *const channel, const uint32_t data_pointer, const XMC_USIC_CH_FIFO_SIZE_t size, const uint32_t limit)

void	XMC_USIC_CH_RXFIFO_DisableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_RXFIFO_EnableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_RXFIFO_Flush (XMC_USIC_CH_t *const channel)

uint16_t	XMC_USIC_CH_RXFIFO_GetData (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_RXFIFO_GetEvent (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_RXFIFO_GetLevel (XMC_USIC_CH_t *const channel)

bool	XMC_USIC_CH_RXFIFO_IsEmpty (XMC_USIC_CH_t *const channel)

bool	XMC_USIC_CH_RXFIFO_IsFull (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_RXFIFO_SetInterruptNodePointer (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, const uint32_t service_request)

void	XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_FIFO_SIZE_t size, const uint32_t limit)

void	XMC_USIC_CH_RXFIFO_SetTriggerLimit (XMC_USIC_CH_t *const channel, const uint32_t limit)

XMC_USIC_CH_STATUS_t	XMC_USIC_CH_SetBaudrate (XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling)

void	XMC_USIC_CH_SetBaudrateDivider (XMC_USIC_CH_t *const channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_t clksel, bool pppen, uint32_t pdiv, XMC_USIC_CH_BRG_CTQSEL_t ctqsel, uint32_t pctq, uint32_t dctq)

XMC_USIC_CH_STATUS_t	XMC_USIC_CH_SetBaudrateEx (XMC_USIC_CH_t *const channel, int32_t rate, int32_t oversampling)

void	XMC_USIC_CH_SetBRGInputClockSource (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_SOURCE_t clock_source)

void	XMC_USIC_CH_SetDataOutputMode (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode)

void	XMC_USIC_CH_SetFractionalDivider (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t mode, const uint16_t step)

void	XMC_USIC_CH_SetFrameLength (XMC_USIC_CH_t *const channel, const uint8_t frame_length)

void	XMC_USIC_CH_SetInputSamplingFreq (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq)

void	XMC_USIC_CH_SetInputSource (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const uint8_t source)

void	XMC_USIC_CH_SetInputTriggerCombinationMode (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)

void	XMC_USIC_CH_SetInterruptNodePointer (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, const uint32_t service_request)

void	XMC_USIC_CH_SetMclkOutputPassiveLevel (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level)

void	XMC_USIC_CH_SetMode (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_OPERATING_MODE_t mode)

void	XMC_USIC_CH_SetPassiveDataLevel (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level)

void	XMC_USIC_CH_SetShiftDirection (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_SHIFT_DIRECTION_t shift_direction)

void	XMC_USIC_CH_SetStartTransmisionMode (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode)

void	XMC_USIC_CH_SetTransmitBufferStatus (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status)

void	XMC_USIC_CH_SetWordLength (XMC_USIC_CH_t *const channel, const uint8_t word_length)

void	XMC_USIC_CH_TriggerServiceRequest (XMC_USIC_CH_t *const channel, const uint32_t service_request_line)

void	XMC_USIC_CH_TXFIFO_ClearEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_TXFIFO_Configure (XMC_USIC_CH_t *const channel, const uint32_t data_pointer, const XMC_USIC_CH_FIFO_SIZE_t size, const uint32_t limit)

void	XMC_USIC_CH_TXFIFO_DisableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_TXFIFO_EnableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_USIC_CH_TXFIFO_Flush (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_TXFIFO_GetEvent (XMC_USIC_CH_t *const channel)

uint32_t	XMC_USIC_CH_TXFIFO_GetLevel (XMC_USIC_CH_t *const channel)

bool	XMC_USIC_CH_TXFIFO_IsEmpty (XMC_USIC_CH_t *const channel)

bool	XMC_USIC_CH_TXFIFO_IsFull (XMC_USIC_CH_t *const channel)

void	XMC_USIC_CH_TXFIFO_PutData (XMC_USIC_CH_t *const channel, const uint16_t data)

void	XMC_USIC_CH_TXFIFO_PutDataEx (XMC_USIC_CH_t *const channel, const uint16_t data, uint8_t loc)

void	XMC_USIC_CH_TXFIFO_PutDataFLEMode (XMC_USIC_CH_t *const channel, const uint16_t data, const uint32_t frame_length)

void	XMC_USIC_CH_TXFIFO_PutDataHPCMode (XMC_USIC_CH_t *const channel, const uint16_t data, const uint32_t frame_length)

void	XMC_USIC_CH_TXFIFO_SetInterruptNodePointer (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, const uint32_t service_request)

void	XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit (XMC_USIC_CH_t *const channel, const XMC_USIC_CH_FIFO_SIZE_t size, const uint32_t limit)

void	XMC_USIC_CH_TXFIFO_SetTriggerLimit (XMC_USIC_CH_t *const channel, const uint32_t limit)

void	XMC_USIC_CH_WriteToTBUF (XMC_USIC_CH_t *const channel, const uint16_t data)

void	XMC_USIC_CH_WriteToTBUFTCI (XMC_USIC_CH_t *const channel, const uint16_t data, const uint32_t transmit_control_information)

void	XMC_USIC_Disable (XMC_USIC_t *const usic)

void	XMC_USIC_Enable (XMC_USIC_t *const usic)

Detailed Description

The Universal Serial Interface Channel(USIC) module is a flexible interface module covering several serial communication protocols. A USIC module contains two independent communication channels named USICx_CH0 and USICx_CH1, with x being the number of the USIC module. The user can program, during run-time, which protocol will be handled by each communication channel and which pins are used. The driver provides APIs, configuration structures and enumerations to configure common features of multiple serial communication protocols.

USIC driver features:

Allows configuration of FIFO for transmit and receive functions.
Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers in a programmer friendly format.
Allows configuration of automatic update for frame length, word length, slave select or slave address.
Allows transmission of data to FIFO using XMC_USIC_CH_TXFIFO_PutData() and XMC_USIC_CH_TXFIFO_PutDataFLEMode()
Allows reading of received data in FIFO using XMC_USIC_CH_RXFIFO_GetData()
Allows configuration of baudrate using XMC_USIC_CH_SetBaudrate()
Provides API to trigger interrupts using XMC_USIC_CH_TriggerServiceRequest()

Macro Definition Documentation

◆ USIC_CH_DXCR_CM_Msk

#define USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk

Common mask for CM bitfield mask in DXnCR register

◆ USIC_CH_DXCR_CM_Pos

#define USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos

Common mask for CM bitfield position in DXnCR register

◆ USIC_CH_DXCR_DFEN_Msk

#define USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk

Common mask for DFEN bitfield mask in DXnCR register

◆ USIC_CH_DXCR_DPOL_Msk

#define USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk

Common mask for DPOL bitfield mask in DXnCR register

◆ USIC_CH_DXCR_DSEL_Msk

#define USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk

Common mask for DSEL bitfield mask in DXnCR register

◆ USIC_CH_DXCR_DSEL_Pos

#define USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos

Common mask for DSEL bitfield position in DXnCR register

◆ USIC_CH_DXCR_DSEN_Msk

#define USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk

Common mask for DSEN bitfield mask in DXnCR register

◆ USIC_CH_DXCR_INSW_Msk

#define USIC_CH_DXCR_INSW_Msk USIC_CH_DX0CR_INSW_Msk

Common mask for INSW bitfield mask in DXnCR register

◆ USIC_CH_DXCR_INSW_pos

#define USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos

Common mask for INSW bitfield position in DXnCR register

◆ USIC_CH_DXCR_SFSEL_Msk

#define USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk

Common mask for SFSEL bitfield mask in DXnCR register

◆ USIC_CH_DXCR_SFSEL_Pos

#define USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos

Common mask for SFSEL bitfield position in DXnCR register

◆ XMC_USIC0

#define XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE)

USIC0 module base address

◆ XMC_USIC0_CH0

#define XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE)

USIC0 channel 0 base address

◆ XMC_USIC0_CH1

#define XMC_USIC0_CH1 ((XMC_USIC_CH_t *)USIC0_CH1_BASE)

USIC0 channel 1 base address

◆ XMC_USIC1

#define XMC_USIC1 ((XMC_USIC_t *)USIC1_BASE)

USIC1 module base address

◆ XMC_USIC1_CH0

#define XMC_USIC1_CH0 ((XMC_USIC_CH_t *)USIC1_CH0_BASE)

USIC1 channel 0 base address

◆ XMC_USIC1_CH1

#define XMC_USIC1_CH1 ((XMC_USIC_CH_t *)USIC1_CH1_BASE)

USIC1 channel 1 base address

◆ XMC_USIC2

#define XMC_USIC2 ((XMC_USIC_t *)USIC2_BASE)

USIC2 module base address

◆ XMC_USIC2_CH0

#define XMC_USIC2_CH0 ((XMC_USIC_CH_t *)USIC2_CH0_BASE)

USIC2 channel 0 base address

◆ XMC_USIC2_CH1

#define XMC_USIC2_CH1 ((XMC_USIC_CH_t *)USIC2_CH1_BASE)

USIC2 channel 1 base address

Typedef Documentation

◆ XMC_USIC_t

typedef USIC_GLOBAL_TypeDef XMC_USIC_t

USIC module structure

Enumeration Type Documentation

◆ XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t

enum XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t

USIC channel baudrate generator divider mode

Enumerator
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED	Baudrate generator clock divider: Disabled
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL	Baudrate generator clock divider: Normal mode
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL	Baudrate generator clock divider: Fractional mode

◆ XMC_USIC_CH_BRG_CLOCK_SOURCE_t

enum XMC_USIC_CH_BRG_CLOCK_SOURCE_t

USIC channel baudrate generator clock source

Enumerator
XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER	Baudrate generator clock source : Source divider. (Internal clock source)
XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T	Baudrate generator clock source : DX1T. (External clock source)
XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1S	Baudrate generator clock source : DX1S. (External clock source)

◆ XMC_USIC_CH_BRG_CTQSEL_t

enum XMC_USIC_CH_BRG_CTQSEL_t

USIC channel input selection for CTQ

Enumerator
XMC_USIC_CH_BRG_CTQSEL_PDIV	fCTQIN = fPDIV
XMC_USIC_CH_BRG_CTQSEL_PPP	fCTQIN = fPPP
XMC_USIC_CH_BRG_CTQSEL_SCLK	fCTQIN = fSCLK
XMC_USIC_CH_BRG_CTQSEL_MCLK	fCTQIN = fMCLK

◆ XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t

enum XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t

USIC channel baudrate generator master clock passive level

Enumerator
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0	Baudrate generator master clock passive level(idle mode signal level) 0
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1	Baudrate generator master clock passive level((idle mode signal level)) 1

◆ XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t

enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t

USIC channel baudrate generator shift clock output

Enumerator
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK	Baudrate generator shift clock output: SCL.(Internally generated shift clock)
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1	Baudrate generator shift clock output: DX1. (External input shift clock)

◆ XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t

enum XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t

USIC channel baudrate generator shift clock passive level

Enumerator
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED	Shift clock passive level 0, delay disabled
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED	Shift clock passive level 1, delay disabled
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED	Shift clock passive level 0, delay enabled
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED	Shift clock passive level 1, delay enabled

◆ XMC_USIC_CH_DATA_OUTPUT_MODE_t

enum XMC_USIC_CH_DATA_OUTPUT_MODE_t

USIC channel data output mode

Enumerator
XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL	Data output normal mode
XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED	Data output inverted mode

◆ XMC_USIC_CH_EVENT_t

enum XMC_USIC_CH_EVENT_t

USIC channel events

Enumerator
XMC_USIC_CH_EVENT_RECEIVE_START	Receive start event
XMC_USIC_CH_EVENT_DATA_LOST	Data lost event
XMC_USIC_CH_EVENT_TRANSMIT_SHIFT	Transmit shift event
XMC_USIC_CH_EVENT_TRANSMIT_BUFFER	Transmit buffer event
XMC_USIC_CH_EVENT_STANDARD_RECEIVE	Receive event
XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE	Alternate receive event
XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR	Baudrate generator event

◆ XMC_USIC_CH_FIFO_SIZE_t

enum XMC_USIC_CH_FIFO_SIZE_t

USIC channel receive FIFO size

Enumerator
XMC_USIC_CH_FIFO_DISABLED	FIFO Disabled
XMC_USIC_CH_FIFO_SIZE_2WORDS	FIFO size: 2 words
XMC_USIC_CH_FIFO_SIZE_4WORDS	FIFO size: 4 words
XMC_USIC_CH_FIFO_SIZE_8WORDS	FIFO size: 8 words
XMC_USIC_CH_FIFO_SIZE_16WORDS	FIFO size: 16 words
XMC_USIC_CH_FIFO_SIZE_32WORDS	FIFO size: 32 words
XMC_USIC_CH_FIFO_SIZE_64WORDS	FIFO size: 64 words

◆ XMC_USIC_CH_INPUT_COMBINATION_MODE_t

enum XMC_USIC_CH_INPUT_COMBINATION_MODE_t

USIC channel input combination mode

Enumerator
XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED	The trigger activation is disabled.
XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE	A rising edge activates DXnT
XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE	A falling edge activates DXnT
XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES	Both edges activate DXnT

◆ XMC_USIC_CH_INPUT_SAMPLING_FREQ_t

enum XMC_USIC_CH_INPUT_SAMPLING_FREQ_t

USIC channel input source sampling frequency

Enumerator
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH	Use fperiph frequency for input source sampling
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER	Common mask for SFSEL bitfield position in DXnCR register Use fFD(fractional divider) frequency for input source sampling

◆ XMC_USIC_CH_INPUT_t

enum XMC_USIC_CH_INPUT_t

USIC channel inputs

Enumerator
XMC_USIC_CH_INPUT_DX0	DX0 input
XMC_USIC_CH_INPUT_DX1	DX1 input
XMC_USIC_CH_INPUT_DX2	DX2 input
XMC_USIC_CH_INPUT_DX3	DX3 input
XMC_USIC_CH_INPUT_DX4	DX4 input
XMC_USIC_CH_INPUT_DX5	DX5 input

◆ XMC_USIC_CH_INTERRUPT_NODE_POINTER_t

enum XMC_USIC_CH_INTERRUPT_NODE_POINTER_t

USIC channel interrupt node pointers

Enumerator
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT	Node pointer for transmit shift interrupt
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER	Node pointer for transmit buffer interrupt
XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE	Node pointer for receive interrupt
XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE	Node pointer for alternate receive interrupt
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL	Node pointer for protocol related interrupts

◆ XMC_USIC_CH_KERNEL_MODE_t

enum XMC_USIC_CH_KERNEL_MODE_t

USIC channel kernel mode

Enumerator
XMC_USIC_CH_KERNEL_MODE_RUN_0	Run mode 0 (transmission and reception possible)
XMC_USIC_CH_KERNEL_MODE_RUN_1	Run mode 1 (transmission and reception possible)
XMC_USIC_CH_KERNEL_MODE_STOP_0	Stop mode 0 (no transmission, but reception possible)
XMC_USIC_CH_KERNEL_MODE_STOP_1	Stop mode 1 (both transmission and reception not possible)

◆ XMC_USIC_CH_OPERATING_MODE_t

enum XMC_USIC_CH_OPERATING_MODE_t

USIC channel operating mode

Enumerator
XMC_USIC_CH_OPERATING_MODE_IDLE	USIC channel idle
XMC_USIC_CH_OPERATING_MODE_SPI	SPI mode
XMC_USIC_CH_OPERATING_MODE_UART	UART mode
XMC_USIC_CH_OPERATING_MODE_I2S	I2S mode
XMC_USIC_CH_OPERATING_MODE_I2C	I2C mode

◆ XMC_USIC_CH_PARITY_MODE_t

enum XMC_USIC_CH_PARITY_MODE_t

USIC channel parity mode

Enumerator
XMC_USIC_CH_PARITY_MODE_NONE	Disable parity mode
XMC_USIC_CH_PARITY_MODE_EVEN	Enable even parity mode
XMC_USIC_CH_PARITY_MODE_ODD	Enable odd parity mode

◆ XMC_USIC_CH_PASSIVE_DATA_LEVEL_t

enum XMC_USIC_CH_PASSIVE_DATA_LEVEL_t

USIC channel output signal passive data level

Enumerator
XMC_USIC_CH_PASSIVE_DATA_LEVEL0	Passive level(idle mode signal level) 0
XMC_USIC_CH_PASSIVE_DATA_LEVEL1	Passive level(idle mode signal level) 1

◆ XMC_USIC_CH_RBUF_STATUS_t

enum XMC_USIC_CH_RBUF_STATUS_t

USIC channel receive buffer status

Enumerator
XMC_USIC_CH_RBUF_STATUS_DATA_VALID0	RBUF0 data has not yet been read out
XMC_USIC_CH_RBUF_STATUS_DATA_VALID1	RBUF1 data has not yet been read out

◆ XMC_USIC_CH_RXFIFO_EVENT_CONF_t

enum XMC_USIC_CH_RXFIFO_EVENT_CONF_t

USIC channel receive FIFO event configuration

Enumerator
XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD	Enable FIFO standard receive interrupt
XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR	Enable receive FIFO error interrupt
XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE	Enable FIFO alternative receive interrupt

◆ XMC_USIC_CH_RXFIFO_EVENT_t

enum XMC_USIC_CH_RXFIFO_EVENT_t

USIC channel receive FIFO status

Enumerator
XMC_USIC_CH_RXFIFO_EVENT_STANDARD	Receive FIFO status: Standard event
XMC_USIC_CH_RXFIFO_EVENT_ERROR	Receive FIFO status: Error event
XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE	Receive FIFO status: Alternative event

◆ XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t

enum XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t

USIC channel receive FIFO interrupt node pointers

Enumerator
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD	Node pointer for FIFO standard receive interrupt
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE	Node pointer for FIFO alternative receive interrupt

◆ XMC_USIC_CH_SHIFT_DIRECTION_t

enum XMC_USIC_CH_SHIFT_DIRECTION_t

USIC channel shift direction. Defines the shift direction of the data words for transmission and reception

Enumerator
XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST	Shift LSB first. The first data bit of a data word is located at bit position 0.
XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST	Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length.

◆ XMC_USIC_CH_START_TRANSMISION_MODE_t

enum XMC_USIC_CH_START_TRANSMISION_MODE_t

USIC channel data transmission start modes. Data shifted out of the transmit pin depends on the value configured for the TDEN bitfield of the TCSR register. Following enum values are used for configuring the TCSR->TDEN bitfield.

Enumerator
XMC_USIC_CH_START_TRANSMISION_DISABLED	Passive data level is sent out on transmission.
XMC_USIC_CH_START_TRANSMISION_ON_TDV	Transmission of the data word in TBUF can be started if TDV = 1
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0	Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_0
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1	Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_1

◆ XMC_USIC_CH_STATUS_t

enum XMC_USIC_CH_STATUS_t

USIC channel driver status

Enumerator
XMC_USIC_CH_STATUS_OK	USIC driver status : OK
XMC_USIC_CH_STATUS_ERROR	USIC driver status : ERROR
XMC_USIC_CH_STATUS_BUSY	USIC driver status : BUSY

◆ XMC_USIC_CH_TBUF_STATUS_SET_t

enum XMC_USIC_CH_TBUF_STATUS_SET_t

USIC channel data transmit buffer status modification

Enumerator
XMC_USIC_CH_TBUF_STATUS_SET_BUSY	Set Transfer buffer status to busy
XMC_USIC_CH_TBUF_STATUS_SET_IDLE	Set Transfer buffer status to idle

◆ XMC_USIC_CH_TBUF_STATUS_t

enum XMC_USIC_CH_TBUF_STATUS_t

USIC channel data transmit buffer status

Enumerator
XMC_USIC_CH_TBUF_STATUS_IDLE	Transfer buffer is currently idle
XMC_USIC_CH_TBUF_STATUS_BUSY	Transfer buffer is currently busy

◆ XMC_USIC_CH_TXFIFO_EVENT_CONF_t

enum XMC_USIC_CH_TXFIFO_EVENT_CONF_t

USIC channel transmit FIFO event configuration

Enumerator
XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD	Enable FIFO standard transmit interrupt
XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR	Enable transmit FIFO error interrupt

◆ XMC_USIC_CH_TXFIFO_EVENT_t

enum XMC_USIC_CH_TXFIFO_EVENT_t

USIC channel transmit FIFO status

Enumerator
XMC_USIC_CH_TXFIFO_EVENT_STANDARD	Transmit FIFO status: Standard event
XMC_USIC_CH_TXFIFO_EVENT_ERROR	Transmit FIFO status: Error event

◆ XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t

enum XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t

USIC channel transmit FIFO interrupt node pointers

Enumerator
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD	Node pointer for FIFO standard transmit interrupt
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE	Node pointer for transmit FIFO error interrupt

Function Documentation

◆ XMC_USIC_CH_ConfigExternalInputSignalToBRG()

void XMC_USIC_CH_ConfigExternalInputSignalToBRG	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	pdiv,
		const uint32_t	oversampling,
		const XMC_USIC_CH_INPUT_COMBINATION_MODE_t	combination_mode
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
pdiv	Desired divider for the external frequency input. Range: minimum value = 1, maximum value = 1024
oversampling	Required oversampling. The value indicates the number of time quanta for one symbol of data. This can be related to the number of samples for each logic state of the data signal. Range: 1 to 32. Value should be chosen based on the protocol used.
combination_mode	Selects which edge of the synchronized(and optionally filtered) signal DXnS actives the trigger output DXnT of the input stage.

Returns: None

Description: Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and the combination mode of the USIC channel.

Related APIs:: XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode()

◆ XMC_USIC_CH_ConfigureShiftClockOutput()

void XMC_USIC_CH_ConfigureShiftClockOutput	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t	passive_level,
		const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t	clock_output
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
passive_level	Passive level for the clock output. Range: XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED,
clock_output	Shift clock source selection. Range: Use XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1

Returns: None

Description: Sets the idle mode shift clock output level and selects the shift clock source.

Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a delay of half shift clock period. Both the configurations are available as enumeration values defined with type XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t. This value should be configured based on the slave device requirement. Shift clock source can be selected between internal clock(master) and external input(slave).

◆ XMC_USIC_CH_ConnectInputDataShiftToDataInput()

void XMC_USIC_CH_ConnectInputDataShiftToDataInput	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: The input of the data shift unit is connected to the selected data input line.

This setting is used if the signals are directly derived from an input pin without treatment by the protocol preprocessor.

Related APIs:: XMC_USIC_CH_ConnectInputDataShiftToPPP()

< Common mask for INSW bitfield mask in DXnCR register

◆ XMC_USIC_CH_ConnectInputDataShiftToPPP()

void XMC_USIC_CH_ConnectInputDataShiftToPPP	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: The input of the data shift unit is controlled by the protocol pre-processor.

Related APIs:: XMC_USIC_CH_ConnectInputDataShiftToDataInput()

< Common mask for INSW bitfield mask in DXnCR register

◆ XMC_USIC_CH_Disable()

void XMC_USIC_CH_Disable ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables the USIC channel.

USIC channel is disabled by setting the module enable bit(MDEN) to 0 in the register KSCFG.

Related APIs:: XMC_USIC_CH_Enable(), XMC_USIC_Disable()

◆ XMC_USIC_CH_DisableDelayCompensation()

void XMC_USIC_CH_DisableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables delay compensation..

Related APIs:: XMC_USIC_CH_EnableDelayCompensation()

◆ XMC_USIC_CH_DisableEvent()

void XMC_USIC_CH_DisableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Bit mask of the channel events to be disabled. Use XMC_USIC_CH_EVENT_t for the bit masks. Range: XMC_USIC_CH_EVENT_RECEIVE_START, XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events can be combined using OR operation.

Returns: None

Description: Disable the channel interrupt events.

Multiple events can be combined using the bitwise OR operation and configured in one function call. XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API.

Related APIs:: XMC_USIC_CH_EnableEvent(), XMC_USIC_CH_SetInterruptNodePointer()

◆ XMC_USIC_CH_DisableFrameLengthControl()

void XMC_USIC_CH_DisableFrameLengthControl ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables automatic update of frame length.

When automatic update of frame length is disabled, frame length has to configured explicitly. Frame length remains fixed until it is changed again.

Related APIs:: XMC_USIC_CH_EnableFrameLengthControl(), XMC_USIC_CH_SetFrameLength()

◆ XMC_USIC_CH_DisableInputDigitalFilter()

void XMC_USIC_CH_DisableInputDigitalFilter	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Disables the input digital filter for USIC channel input data signal.

Input data signal from the selected multiplexer will not be digitally filtered.

Related APIs:: XMC_USIC_CH_EnableInputDigitalFilter()

< Common mask for DFEN bitfield mask in DXnCR register

◆ XMC_USIC_CH_DisableInputInversion()

void XMC_USIC_CH_DisableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Disables input inversion for USIC channel.

Resets the input data polarity for the USIC channel input data signal.

Related APIs:: XMC_USIC_CH_EnableInputInversion()

< Common mask for DPOL bitfield mask in DXnCR register

◆ XMC_USIC_CH_DisableInputSync()

void XMC_USIC_CH_DisableInputSync	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Disables input synchronization for the USIC channel input data signal.

Input data signal from the selected multiplexer will not be synchronized.

Related APIs:: XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_DisableInputDigitalFilter()

< Common mask for DSEN bitfield mask in DXnCR register

◆ XMC_USIC_CH_DisableTBUFDataValidTrigger()

void XMC_USIC_CH_DisableTBUFDataValidTrigger ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables the trigger of TDV depending on DX2T signal.

Bit TCSR.TE is permanently set.

Related APIs:: XMC_USIC_CH_EnableTBUFDataValidTrigger()

◆ XMC_USIC_CH_DisableTimeMeasurement()

void XMC_USIC_CH_DisableTimeMeasurement ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables time measurement using the capture mode timer.

Time measurement is disabled by clearing the timer enable flag in BRG register.

Related APIs:: XMC_USIC_CH_EnableTimeMeasurement()

◆ XMC_USIC_CH_DisableWordLengthControl()

void XMC_USIC_CH_DisableWordLengthControl ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Disables automatic update of word length.

When automatic update of word length is disabled, word length has to configured explicitly. Word length remains fixed until it is changed again.

Related APIs:: XMC_USIC_CH_EnableFrameLengthControl(), XMC_USIC_CH_SetWordLength()

◆ XMC_USIC_CH_Enable()

void XMC_USIC_CH_Enable ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Enables the USIC channel.

USIC channel is enabled by setting the module enable bit in KSCFG register bitfield MODEN. On enabling, the channel is set to idle mode.

Related APIs:: XMC_USIC_CH_Disable(), XMC_USIC_Enable()

◆ XMC_USIC_CH_EnableDelayCompensation()

void XMC_USIC_CH_EnableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Enables delay compensation.

Delay compensation can be applied to the receive path.

Related APIs:: XMC_USIC_CH_DisableDelayCompensation()

◆ XMC_USIC_CH_EnableEvent()

void XMC_USIC_CH_EnableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Bit mask of the channel events to be enabled. Use XMC_USIC_CH_EVENT_t for the bit masks. Range: XMC_USIC_CH_EVENT_RECEIVE_START, XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events can be combined using OR operation.

Returns: None

Description: Enable the channel interrupt events.

Common channel events related to serial communication can be configured using this API. Multiple events can be combined using the bitwise OR operation and configured in one function call. XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API.

Related APIs:: XMC_USIC_CH_DisableEvent(), XMC_USIC_CH_SetInterruptNodePointer()

◆ XMC_USIC_CH_EnableFrameLengthControl()

void XMC_USIC_CH_EnableFrameLengthControl ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Enables automatic update of frame length.

When the automatic update of frame length is enabled, frame length is configured based on the index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], frame length is configured with the mask value of x at the last 5 bit positions. Same logic is applicable if data is written to IN[x] register.

Related APIs:: XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode()

◆ XMC_USIC_CH_EnableInputDigitalFilter()

void XMC_USIC_CH_EnableInputDigitalFilter	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Enables the input digital filter for USIC channel input data signal.

Input data signal from the selected multiplexer will be digitally filtered.

Related APIs:: XMC_USIC_CH_DisableInputDigitalFilter()

< Common mask for DFEN bitfield mask in DXnCR register

◆ XMC_USIC_CH_EnableInputInversion()

void XMC_USIC_CH_EnableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Enables input inversion for USIC channel input data signal.

Polarity of the input source can be changed to provide inverted data input.

Related APIs:: XMC_USIC_CH_DisableInputInversion()

< Common mask for DPOL bitfield mask in DXnCR register

◆ XMC_USIC_CH_EnableInputSync()

void XMC_USIC_CH_EnableInputSync	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

Returns: None

Description: Enables input synchronization for the USIC channel input data signal.

Input data signal from the selected multiplexer will be synchronized with fPERIPH. A noisy signal can be synchronized and filtered by enabling the digital filter.

Related APIs:: XMC_USIC_CH_DisableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()

< Common mask for DSEN bitfield mask in DXnCR register

◆ XMC_USIC_CH_EnableTBUFDataValidTrigger()

void XMC_USIC_CH_EnableTBUFDataValidTrigger ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Bit TCSR.TE is set if DX2T becomes active while TDV = 1.

Enables the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active for event driven transfer starts.

Related APIs:: XMC_USIC_CH_DisableTBUFDataValidTrigger()

◆ XMC_USIC_CH_EnableTimeMeasurement()

void XMC_USIC_CH_EnableTimeMeasurement ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Enables time measurement using the capture mode timer.

Time measurement is enabled by setting the timer enable flag in BRG register.

Related APIs:: XMC_USIC_CH_DisableTimeMeasurement()

◆ XMC_USIC_CH_EnableWordLengthControl()

void XMC_USIC_CH_EnableWordLengthControl ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Enables automatic update of word length.

When the automatic update of word length is enabled, word length is configured based on the index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], word length is configured with the mask value of x at the last 5 bit positions. Same logic is applicable if data is written to IN[x] register.

Related APIs:: XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode()

◆ XMC_USIC_CH_GetBaudrate()

uint32_t XMC_USIC_CH_GetBaudrate ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: baudrate currently used by USIC channel for .

Description: Calculates the current used baudrate (fCTQIN) of a USIC channel.

Related APIs:: XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx()

◆ XMC_USIC_CH_GetCaptureTimerValue()

uint32_t XMC_USIC_CH_GetCaptureTimerValue ( const XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Captured counter value

Description: The value of the counter is captured if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage.

◆ XMC_USIC_CH_GetMCLKFrequency()

uint32_t XMC_USIC_CH_GetMCLKFrequency ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: baudrate currently used by USIC channel.

Description: Calculates the current used MCLK frequency of a USIC channel.

Related APIs:: XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx()

◆ XMC_USIC_CH_GetReceiveBufferStatus()

uint32_t XMC_USIC_CH_GetReceiveBufferStatus ( XMC_USIC_CH_t *const channel )

API to get receive buffer status.

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status of data validity check for RBUF0 and RBUF1.
Returned value should be masked with RDV0 and RDV1 bits to know the status.
Range: XMC_USIC_CH_RBUF_STATUS_DATA_VALID0, XMC_USIC_CH_RBUF_STATUS_DATA_VALID1.

Description: Checks if RBUF0 and RBUF1 have valid unread data.

It checks the bits RDV0 and RDV1 of the RBUFSR register. Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1. It can be used to decide whether 2bytes has to be read from RBUF or 1 byte. If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 are set, then 2 bytes can be read from RBUF. If only either of them is set, then only one byte can be read from RBUF.

Related APIs:: XMC_USIC_CH_GetTransmitBufferStatus()

◆ XMC_USIC_CH_GetSCLKFrequency()

uint32_t XMC_USIC_CH_GetSCLKFrequency ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: baudrate currently used by USIC channel.

Description: Calculates the current used SCLK frequency of a USIC channel.

Related APIs:: XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx()

◆ XMC_USIC_CH_GetTransmitBufferStatus()

XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Stataus XMC_USIC_CH_TBUF_STATUS_IDLE if transmit buffer is free, XMC_USIC_CH_TBUF_STATUS_BUSY if transmit buffer is busy.

Description: Gets transmit buffer status.

Status indicates whether the transmit buffer is free, or busy transmitting data. The status depends on the value of TDV flag in TCSR register. This status can be used while transmitting data. Transmit data when the transmit buffer status is XMC_USIC_CH_TBUF_STATUS_IDLE.

Related APIs:: XMC_USIC_CH_SetDataOutputMode()

◆ XMC_USIC_CH_InvalidateReadData()

void XMC_USIC_CH_InvalidateReadData ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software.

Related APIs:: XMC_USIC_CH_GetTransmitBufferStatus()

◆ XMC_USIC_CH_RXFIFO_ClearEvent()

void XMC_USIC_CH_RXFIFO_ClearEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Receive FIFO events to be cleared. Range: XMC_USIC_CH_RXFIFO_EVENT_STANDARD, XMC_USIC_CH_RXFIFO_EVENT_ERROR, XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.

Returns: None

Description: Clears the receive FIFO event flags in the status register.

USIC channel peripheral does not clear the event flags after they are read. This API clears the events provided in the mask value. XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events can be cleared by providing a mask value obtained by bitwise OR operation of multiple event enumerations.

Related APIs:: XMC_USIC_CH_RXFIFO_GetEvent()

◆ XMC_USIC_CH_RXFIFO_Configure()

void XMC_USIC_CH_RXFIFO_Configure	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	data_pointer,
		const XMC_USIC_CH_FIFO_SIZE_t	size,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data_pointer	Start position inside the FIFO buffer. Range: 0 to 63.
size	Required size of the receive FIFO. Range: XMC_USIC_CH_FIFO_DISABLED, XMC_USIC_CH_FIFO_SIZE_2WORDS.. XMC_USIC_CH_FIFO_SIZE_64WORDS
limit	Threshold of receive FIFO filling level to be considered for generating events. Range: 0 to size -1.

Returns: None

Description: Configures the receive FIFO.

Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. Each channel can share the FIFO for transmission and reception. data_pointer represents the start index in the common FIFO, from where received data can be put. size represents the size of receive FIFO as a multiple of 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard receive buffer event or alternative receive buffer event is generated when the FIFO filling level exceeds the limit value.

Related APIs:: XMC_USIC_CH_RXFIFO_EnableEvent(), XMC_USIC_CH_RXFIFO_SetInterruptNodePointer()

◆ XMC_USIC_CH_RXFIFO_DisableEvent()

void XMC_USIC_CH_RXFIFO_DisableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Events to be disabled. Range: XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR, XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE.

Returns: None

Description: Disables the selected interrupt events related to receive FIFO.

By disabling the interrupt events, generation of interrupt is stopped. User can poll the event flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent(). Event bitmasks can be constructed using the enumeration XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing multiple events, combine the events using bitwise OR operation.

Related APIs:: XMC_USIC_CH_RXFIFO_GetEvent(), XMC_USIC_CH_RXFIFO_EnableEvent()

◆ XMC_USIC_CH_RXFIFO_EnableEvent()

void XMC_USIC_CH_RXFIFO_EnableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Events to be enabled. Multiple events can be bitwise OR combined. XMC_USIC_CH_RXFIFO_EVENT_CONF_t

Returns: None

Description: Enables the interrupt events related to transmit FIFO.

Event bitmasks can be constructed using the enumeration XMC_USIC_CH_RXFIFO_EVENT_CONF_t. Multiple events can be enabled by providing multiple events in a single call. For providing multiple events, combine the events using bitwise OR operation.

Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node must be enabled.

Related APIs:: XMC_USIC_CH_RXFIFO_SetInterruptNodePointer()

◆ XMC_USIC_CH_RXFIFO_Flush()

void XMC_USIC_CH_RXFIFO_Flush ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Clears the contents of receive FIFO.

Receive FIFO contents will be cleared and the filling level will be reset to 0.

Related APIs:: XMC_USIC_CH_RXFIFO_GetLevel()

◆ XMC_USIC_CH_RXFIFO_GetData()

uint16_t XMC_USIC_CH_RXFIFO_GetData ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Value read from the receive FIFO.
Range: 16bit data. Length of data depends on the word length configuration.

Description: Gets data from the receive FIFO.

Receive FIFO should be read only if data is availble in the FIFO. This can be checked using the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an attempt is made to read from an empty receive FIFO. To read all the received data, user should keep reading data until receive FIFO is empty.

Related APIs:: XMC_USIC_CH_RXFIFO_ClearEvent()

◆ XMC_USIC_CH_RXFIFO_GetEvent()

uint32_t XMC_USIC_CH_RXFIFO_GetEvent ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status of standard receive buffer, alternative receive buffer and receive buffer error events.
Range: XMC_USIC_CH_RXFIFO_EVENT_STANDARD, XMC_USIC_CH_RXFIFO_EVENT_ERROR, XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.

Description: Gets the receive FIFO events' status.

Gives the status of receive FIFO standard receive buffer event, alternative receive buffer event and receive buffer error event. The status bits are located at their bitpositions in the TRBSR register in the returned value. User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the status of return value. The status can be found by using the bitwise AND operation on the returned value with the enumerated value.

Note: Event status flags should be cleared by the user explicitly.

Related APIs:: XMC_USIC_CH_RXFIFO_ClearEvent()

◆ XMC_USIC_CH_RXFIFO_GetLevel()

uint32_t XMC_USIC_CH_RXFIFO_GetLevel ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: uint32_t Receive FIFO filling level.
Range: minimum= 0(FIFO empty), maximum= receive FIFO size.

Description: Gets the receive FIFO filling level.

For every word received, the filling level is incremented. The API gives the value of this filling level. The filling level is decremented when the data is read out of the receive FIFO.

Related APIs:: XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData()

◆ XMC_USIC_CH_RXFIFO_IsEmpty()

bool XMC_USIC_CH_RXFIFO_IsEmpty ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status true if receive FIFO is empty, false if receive FIFO has some data.

Description: Checks if receive FIFO is empty.

When the receive FIFO is empty, received data will be put in receive FIFO. When the last received word in the FIFO is read, FIFO empty flag is set. Any attempt to read from an empty receive FIFO will set the receive FIFO error flag.

Related APIs:: XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData()

◆ XMC_USIC_CH_RXFIFO_IsFull()

bool XMC_USIC_CH_RXFIFO_IsFull ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status true if receive FIFO is full false if receive FIFO is not full.

Description: Checks if receive FIFO is full.

When the receive FIFO filling level reaches the configured size, FIFO full flag is set. Any data received when the receive FIFO is full, is lost.

Related APIs:: XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush()

◆ XMC_USIC_CH_RXFIFO_SetInterruptNodePointer()

void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t	interrupt_node,
		const uint32_t	service_request
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
interrupt_node	Node pointer representing the receive FIFO events. Range: XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
service_request	The service request to be used for interrupt generation. Range: 0 to 5.

Returns: None

Description: Sets an interrupt node for the receive FIFO events.

A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used among the 6 interrupt nodes available for USIC module. API configures the service request to be used for interrupt generation for the events selected. A receive FIFO event can generate an interrupt only if the interrupt node is configured for the event and the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer interrupt is generated if the interrupt node for the same is set and interrupt is enabled.

Note: NVIC node should be explicitly enabled for the interrupt generation.

Related APIs:: XMC_USIC_CH_RXFIFO_EnableEvent()

◆ XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit()

void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_FIFO_SIZE_t	size,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
size	Required size of the receive FIFO. Range: XMC_USIC_CH_FIFO_DISABLED, XMC_USIC_CH_FIFO_SIZE_2WORDS.. XMC_USIC_CH_FIFO_SIZE_64WORDS
limit	Threshold for receive FIFO filling level to be considered for generating events. Range: 0 to size -1.

Returns: None

Deprecated:: { Use XMC_USIC_CH_RXFIFO_SetTriggerLimit() }

Description: Sets the size and trigger limit for the receive FIFO.

The API is not to be called for initializing the receive FIFO. The API shall be used for the runtime change of receive FIFO trigger limit. FIFO start position will not be affected on execution.

Related APIs:: XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n

◆ XMC_USIC_CH_RXFIFO_SetTriggerLimit()

void XMC_USIC_CH_RXFIFO_SetTriggerLimit	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
limit	Threshold for transmit FIFO filling level to be considered for generating events. Range: 0 to fifo size -1.

Returns: None

Description: Sets the trigger limit for the TX FIFO.

Related APIs:: XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()

◆ XMC_USIC_CH_SetBaudrate()

XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate	(	XMC_USIC_CH_t *const	channel,
		uint32_t	rate,
		uint32_t	oversampling
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
rate	Desired baudrate. Range: minimum value = 100, maximum value depends on the peripheral clock frequency and oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
oversampling	Required oversampling. The value indicates the number of time quanta for one symbol of data. This can be related to the number of samples for each logic state of the data signal. Range: 1 to 32. Value should be chosen based on the protocol used.

Returns: Status indicating the baudrate configuration.
Range: XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.

Description: Configures the baudrate of the USIC channel.

Baudrate is configured by considering the peripheral frequency and the desired baudrate. Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired baudrate.

Related APIs:: XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource()

◆ XMC_USIC_CH_SetBaudrateDivider()

void XMC_USIC_CH_SetBaudrateDivider	(	XMC_USIC_CH_t *const	channel,
		XMC_USIC_CH_BRG_CLOCK_SOURCE_t	clksel,
		bool	pppen,
		uint32_t	pdiv,
		XMC_USIC_CH_BRG_CTQSEL_t	ctqsel,
		uint32_t	pctq,
		uint32_t	dctq
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
clksel	Baudrate generator clock source.
pppen	Enable 2:1 Divider for fPPP.
pdiv	Divider Factor to generate fPDIV = fPPP / (pDIV + 1)
ctqsel	Input selection for CTQ.
pctq	Pre-Divider for Time Quanta Counter. fCTQIN / (PCQT + 1)
dctq	Denominator for Time Quanta Counter. fTQ / (DCTQ + 1)

Returns: None

Description: Configures the baudrate generator of the USIC channel.

Related APIs:: XMC_USIC_CH_SetFractionalDivider()

◆ XMC_USIC_CH_SetBaudrateEx()

XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx	(	XMC_USIC_CH_t *const	channel,
		int32_t	rate,
		int32_t	oversampling
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
rate	Desired baudrate. Only integer dividers of peripheral clock are achievable
oversampling	Required oversampling. The value indicates the number of time quanta for one symbol of data. This can be related to the number of samples for each logic state of the data signal. Range: 1 to 32. Value should be chosen based on the protocol used.

Returns: Status indicating the baudrate configuration.
Range: XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.

Description: Configures the baudrate of the USIC channel using the integer divider which restrics the achievable baudrate but decreses jitter.

Baudrate is configured by considering the peripheral frequency and the desired baudrate. Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired baudrate.

Related APIs:: XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource()

◆ XMC_USIC_CH_SetBRGInputClockSource()

void XMC_USIC_CH_SetBRGInputClockSource	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_BRG_CLOCK_SOURCE_t	clock_source
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
clock_source	clock source for the BRG.

Returns: None

Description: Sets the clock source for the BRG.

Related APIs:: XMC_USIC_CH_SetInputTriggerCombinationMode(), XMC_USIC_CH_SetExternalClockBRGDivider()

◆ XMC_USIC_CH_SetDataOutputMode()

void XMC_USIC_CH_SetDataOutputMode	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_DATA_OUTPUT_MODE_t	data_output_mode
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data_output_mode	Data output mode. Range: XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL, XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED

Returns: None

Description: Configures the mode for data output.

USIC channel can be configured to shift inverted data or direct data based on the input to the API.

Related APIs:: XMC_USIC_CH_SetStartTransmisionMode()

◆ XMC_USIC_CH_SetFractionalDivider()

void XMC_USIC_CH_SetFractionalDivider	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t	mode,
		const uint16_t	step
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
mode	divider mode XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t
step	divider XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL resulting divider = 1023 - step XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL resulting divider = 1023 / step

Returns: None

Description: The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024.

◆ XMC_USIC_CH_SetFrameLength()

void XMC_USIC_CH_SetFrameLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	frame_length
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
frame_length	Number of bits in a frame. Range: minimum= 1, maximum= 0x3f. The maximum value for fixed frame size is 0x3f. e.g: For a frame length of 16, frame_length should be provided as 16.

Returns: None

Description: Define the data frame length.

Set the number of bits to be serially transmitted in a frame. The frame length should be multiples of word length. If the value is set to 0x40, the frame length has to be controlled explicitly.

Related APIs:: XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl()

◆ XMC_USIC_CH_SetInputSamplingFreq()

void XMC_USIC_CH_SetInputSamplingFreq	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input,
		const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t	sampling_freq
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support..
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5
sampling_freq	Sampling frequency value of type XMC_USIC_CH_INPUT_SAMPLING_FREQ_t.

Returns: None

Description: Sets sampling frequency for USIC channel input data signal.

Related APIs:: XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()

< Common mask for SFSEL bitfield mask in DXnCR register

◆ XMC_USIC_CH_SetInputSource()

void XMC_USIC_CH_SetInputSource	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input,
		const uint8_t	source
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

input USIC channel input stage of type XMC_USIC_CH_INPUT_t.
Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5

source

Input source select for the input stage. The table below maps the enum value with the input channel.

0	DXnA
1	DXnB
2	DXnC
3	DXnD
4	DXnE
5	DXnF
6	DXnG
7	Always 1

Returns: None

Description: Selects the data source for USIC input stage.

Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages like DX0CR, DX1CR etc.

Related APIs:: XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_SetInputSamplingFreq()

< Common mask for DSEL bitfield mask in DXnCR register

< Common mask for DSEL bitfield position in DXnCR register

◆ XMC_USIC_CH_SetInputTriggerCombinationMode()

void XMC_USIC_CH_SetInputTriggerCombinationMode	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INPUT_t	input,
		const XMC_USIC_CH_INPUT_COMBINATION_MODE_t	combination_mode
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support..
input	USIC channel input stage of type XMC_USIC_CH_INPUT_t. Range: XMC_USIC_CH_INPUT_DX0 to XMC_USIC_CH_INPUT_DX5
combination_mode	Combination mode value of type XMC_USIC_CH_INPUT_COMBINATION_MODE_t.

Returns: None

Description: Selects which edge of the synchronized signal DXnS activates the trigger output DXnT of the input stage.

Related APIs:: XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()

< Common mask for CM bitfield mask in DXnCR register

< Common mask for CM bitfield position in DXnCR register

◆ XMC_USIC_CH_SetInterruptNodePointer()

void XMC_USIC_CH_SetInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t	interrupt_node,
		const uint32_t	service_request
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
interrupt_node	Interrupt node pointer to be configured. Range: XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
service_request	Service request number. Range: 0 to 5.

Returns: None

Description: Sets the interrupt node for USIC channel events.

For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). The NVIC node gets linked to the interrupt event by doing so.
Note: NVIC node should be separately enabled to generate the interrupt.

Related APIs:: XMC_USIC_CH_EnableEvent()

◆ XMC_USIC_CH_SetMclkOutputPassiveLevel()

void XMC_USIC_CH_SetMclkOutputPassiveLevel	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t	passive_level
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
passive_level	Passive level for the master clock output. Range: XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0, XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1.

Returns: None

Description: Sets the idle mode pin level for the master clock output.

◆ XMC_USIC_CH_SetMode()

void XMC_USIC_CH_SetMode	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_OPERATING_MODE_t	mode
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
mode	USIC channel operation mode. Range: XMC_USIC_CH_OPERATING_MODE_IDLE, XMC_USIC_CH_OPERATING_MODE_SPI, XMC_USIC_CH_OPERATING_MODE_UART, XMC_USIC_CH_OPERATING_MODE_I2S, XMC_USIC_CH_OPERATING_MODE_I2C.

Returns: None

Description: Sets the USIC channel operation mode.

A USIC channel can support multiple serial communication protocols like UART, SPI, I2C and I2S. The API sets the input operation mode to the USIC channel.

Related APIs:: XMC_USIC_Enable(), XMC_USIC_CH_Enable()

◆ XMC_USIC_CH_SetPassiveDataLevel()

void XMC_USIC_CH_SetPassiveDataLevel	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t	passive_level
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
passive_level	Value of passive level for the channel. Range: XMC_USIC_CH_PASSIVE_DATA_LEVEL0, XMC_USIC_CH_PASSIVE_DATA_LEVEL1

Returns: None

Description: Set the passive data level of the output signal.

When the USIC channel transmit stage is idle, the output signal level stays at the configured passive level.

Related APIs:: XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode()

◆ XMC_USIC_CH_SetShiftDirection()

void XMC_USIC_CH_SetShiftDirection	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_SHIFT_DIRECTION_t	shift_direction
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
word_length	Number of bits to be configured for a data word. Range: minimum= 1, maximum= 16. e.g: For word length of 8, word_length should be provided as 8.

Returns: None

Description: Sets the data word length in number of bits.

Sets the number of bits to represent a data word. Frame length should be a multiple of word length.

Related APIs:: XMC_USIC_CH_SetFrameLength()

◆ XMC_USIC_CH_SetStartTransmisionMode()

void XMC_USIC_CH_SetStartTransmisionMode	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_START_TRANSMISION_MODE_t	start_transmision_mode
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
start_transmision_mode	Transmission mode to be enabled. Range: XMC_USIC_CH_START_TRANSMISION_DISABLED, XMC_USIC_CH_START_TRANSMISION_ON_TDV, XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0, XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1

Returns: None

Description: Configures data transmission.

The configuration affects the data shifted on the DOUT0 pin.

Related APIs:: XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode()

◆ XMC_USIC_CH_SetTransmitBufferStatus()

void XMC_USIC_CH_SetTransmitBufferStatus	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_TBUF_STATUS_SET_t	transmit_buffer_status
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
transmit_buffer_status	clearing or setting the TDV flag.

Returns: None

Description: Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software.

Related APIs:: XMC_USIC_CH_GetTransmitBufferStatus()

◆ XMC_USIC_CH_SetWordLength()

void XMC_USIC_CH_SetWordLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	word_length
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
word_length	Number of bits to be configured for a data word. Range: minimum= 1, maximum= 16. e.g: For word length of 8, word_length should be provided as 8.

Returns: None

Description: Sets the data word length in number of bits.

Sets the number of bits to represent a data word. Frame length should be a multiple of word length.

Related APIs:: XMC_USIC_CH_SetFrameLength()

◆ XMC_USIC_CH_TriggerServiceRequest()

void XMC_USIC_CH_TriggerServiceRequest	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	service_request_line
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
service_request_line	service request number of the event to be triggered. Range: 0 to 5.

Returns: None

Description: Trigger a USIC interrupt service request.

When the USIC service request is triggered, the NVIC interrupt associated with it will be generated if enabled.

Related APIs:: XMC_USIC_CH_SetInterruptNodePointer()

◆ XMC_USIC_CH_TXFIFO_ClearEvent()

void XMC_USIC_CH_TXFIFO_ClearEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Transmit FIFO events to be cleared. Range: XMC_USIC_CH_TXFIFO_EVENT_STANDARD, XMC_USIC_CH_TXFIFO_EVENT_ERROR.

Returns: None

Description: Clears the transmit FIFO event flags in the status register.

USIC channel peripheral does not clear the event flags after they are read. This API clears the events provided in the mask value. XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events can be cleared by providing a mask value obtained by bitwise OR operation of multiple event enumerations.

Related APIs:: XMC_USIC_CH_TXFIFO_GetEvent()

◆ XMC_USIC_CH_TXFIFO_Configure()

void XMC_USIC_CH_TXFIFO_Configure	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	data_pointer,
		const XMC_USIC_CH_FIFO_SIZE_t	size,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data_pointer	Start position inside the FIFO buffer. Range: 0 to 63.
size	Required size of the transmit FIFO. Range: XMC_USIC_CH_FIFO_DISABLED, XMC_USIC_CH_FIFO_SIZE_2WORDS.. XMC_USIC_CH_FIFO_SIZE_64WORDS
limit	Threshold of transmit FIFO filling level to be considered for generating events. Range: 0 to size -1.

Returns: None

Description

Initializes the transmit FIFO.

Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. Each channel can share the FIFO for transmission and reception. data_pointer represents the start index in the common FIFO, from where transmit data can be put, for the selected USIC channel. size represents the size of transmit FIFO as a multiple of

Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard transmit buffer event is generated when the FIFO filling level falls below the limit value.

Related APIs:: XMC_USIC_CH_TXFIFO_EnableEvent(), XMC_USIC_CH_TXFIFO_SetInterruptNodePointer()

◆ XMC_USIC_CH_TXFIFO_DisableEvent()

void XMC_USIC_CH_TXFIFO_DisableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Events to be disabled. XMC_USIC_CH_TXFIFO_EVENT_CONF_t

Returns: None

Description: Disables the interrupt events related to transmit FIFO.

By disabling the interrupt events, generation of interrupt is stopped. User can poll the event flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent(). Event bitmasks can be constructed using the enumeration XMC_USIC_CH_TXFIFO_EVENT_CONF_t. For providing multiple events, combine the events using bitwise OR operation.

Related APIs:: XMC_USIC_CH_TXFIFO_GetEvent(), XMC_USIC_CH_TXFIFO_EnableEvent()

◆ XMC_USIC_CH_TXFIFO_EnableEvent()

void XMC_USIC_CH_TXFIFO_EnableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
event	Events to be enabled. Multiple events can be bitwise OR combined. XMC_USIC_CH_TXFIFO_EVENT_CONF_t

Returns: None

Description: Enables the interrupt events related to transmit FIFO.

Event bitmasks can be constructed using the enumeration XMC_USIC_CH_TXFIFO_EVENT_CONF_t. Multiple events can be enabled by providing multiple events in a single call. For providing multiple events, combine the events using bitwise OR operation. Events are configured in the TBCTR register.

Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node must be enabled.

Related APIs:: XMC_USIC_CH_TXFIFO_SetInterruptNodePointer()

◆ XMC_USIC_CH_TXFIFO_Flush()

void XMC_USIC_CH_TXFIFO_Flush ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: None

Description: Clears the contents of transmit FIFO.

Transmit FIFO contents will be cleared and the filling level will be reset to 0.

Related APIs:: XMC_USIC_CH_TXFIFO_GetLevel()

◆ XMC_USIC_CH_TXFIFO_GetEvent()

uint32_t XMC_USIC_CH_TXFIFO_GetEvent ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status of standard transmit and transmit buffer error events. XMC_USIC_CH_TXFIFO_EVENT_t

Description: Gets the transmit FIFO event status.

Gives the status of transmit FIFO standard transmit buffer event and transmit buffer error event. The status bits are located at their bit positions in the TRBSR register in the returned value. User can make use of the XMC_USIC_CH_TXFIFO_EVENT_t enumeration for checking the status of return value. The status can be found by using the bitwise AND operation on the returned value with the enumerated value.

Note: Event status flags should be cleared by the user explicitly.

Related APIs:: XMC_USIC_CH_TXFIFO_ClearEvent()

◆ XMC_USIC_CH_TXFIFO_GetLevel()

uint32_t XMC_USIC_CH_TXFIFO_GetLevel ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Transmit FIFO filling level.
Range: minimum= 0(FIFO empty), maximum= transmit FIFO size.

Description: Gets the transmit FIFO filling level.

For every word written to the FIFO, filling level is updated. The API gives the value of this filling level.

Related APIs:: XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData()

◆ XMC_USIC_CH_TXFIFO_IsEmpty()

bool XMC_USIC_CH_TXFIFO_IsEmpty ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status true if transmit FIFO is empty false if transmit FIFO has some data.

Description: Checks if transmit FIFO is empty.

When the transmit FIFO is empty, data can be written to FIFO. When the last written word to the transmit FIFO is transmitted out of the FIFO, FIFO empty flag is set.

Related APIs:: XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData()

◆ XMC_USIC_CH_TXFIFO_IsFull()

bool XMC_USIC_CH_TXFIFO_IsFull ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.

Returns: Status true if transmit FIFO is full false if transmit FIFO is not full.

Description: Checks if transmit FIFO is full.

When the transmit FIFO filling level reaches the configured size, FIFO full flag is set. User should not write to the FIFO when the transmit FIFO is full.

Related APIs:: XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush()

◆ XMC_USIC_CH_TXFIFO_PutData()

void XMC_USIC_CH_TXFIFO_PutData	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted. Range: 16bit unsigned data. minimum= 0, maximum= 65535

Returns: None

Description: Writes data into the transmit FIFO.

The data provided is placed in the transmit FIFO. The transmit FIFO should be configured before calling this API.

Related APIs:: XMC_USIC_CH_TXFIFO_EnableEvent()

◆ XMC_USIC_CH_TXFIFO_PutDataEx()

void XMC_USIC_CH_TXFIFO_PutDataEx	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		uint8_t	loc
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted. Range: 16bit unsigned data. minimum= 0, maximum= 65535
loc	Input location.

Returns: None

Description: Transmit data can be loaded to TBUF by software by writing to the transmit buffer input locations TBUFx (x = 00-31), consisting of 32 consecutive addresses. The data written to one of these input locations is stored in the transmit buffer TBUF. Additionally, the address of the written location is evaluated and can be used for additional control purposes. This 5-bit wide information (named Transmit Control Information TCI) can be used for different purposes in different protocols.

Related APIs:: XMC_USIC_CH_EnableWordLengthControl()
XMC_USIC_CH_EnableFrameLengthControl()

◆ XMC_USIC_CH_TXFIFO_PutDataFLEMode()

void XMC_USIC_CH_TXFIFO_PutDataFLEMode	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		const uint32_t	frame_length
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted.
frame_length	Frame length to be configured while transmitting the data. Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set frame_length as 15.

Returns: None

Description: Writes data to the transmit FIFO in frame length control mode.

When frame length control is enabled for dynamic update of frame length, this API can be used. frame_length represents the frame length to be updated by the peripheral. frame_length is used as index for the IN[] register array.

Related APIs:: XMC_USIC_CH_TXFIFO_PutDataEx()
XMC_USIC_CH_EnableFrameLengthControl()

◆ XMC_USIC_CH_TXFIFO_PutDataHPCMode()

void XMC_USIC_CH_TXFIFO_PutDataHPCMode	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		const uint32_t	frame_length
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted.
frame_length	Frame length to be configured while transmitting the data. Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set frame_length as 15.

Returns: None

Description: Writes data to the transmit FIFO in hardware port control mode.

When hardware port control is enabled for dynamic update of frame length, this API can be used. frame_length represents the frame length to be updated by the peripheral. frame_length is used as index for the IN[] register array.

Related APIs:: XMC_USIC_CH_EnableFrameLengthControl()

◆ XMC_USIC_CH_TXFIFO_SetInterruptNodePointer()

void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t	interrupt_node,
		const uint32_t	service_request
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
interrupt_node	Node pointer representing the transmit FIFO events. Range: XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
service_request	The service request to be used for interrupt generation. Range: 0 to 5.

Returns: None

Description: Sets an interrupt node for the transmit FIFO events.

A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used among the 6 interrupt nodes available for USIC module. API configures the service request to be used for interrupt generation for the events selected. A transmit FIFO event can generate an interrupt only if the interrupt node is configured for the event and the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer interrupt is generated if the interrupt node for the same is set and interrupt is enabled.

Note: NVIC node should be explicitly enabled for the interrupt generation.

Related APIs:: XMC_USIC_CH_TXFIFO_EnableEvent()

◆ XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()

void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit	(	XMC_USIC_CH_t *const	channel,
		const XMC_USIC_CH_FIFO_SIZE_t	size,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
size	Required size of the transmit FIFO. Range: XMC_USIC_CH_FIFO_DISABLED, XMC_USIC_CH_FIFO_SIZE_2WORDS.. XMC_USIC_CH_FIFO_SIZE_64WORDS
limit	Threshold for transmit FIFO filling level to be considered for generating events. Range: 0 to size -1.

Returns: None

Deprecated:: { Use XMC_USIC_CH_TXFIFO_SetTriggerLimit() }

Description: Sets the size and trigger limit for the transmit FIFO.

The API is not to be called for initializing the transmit FIFO. The API shall be used for the runtime change of transmit FIFO trigger limit. FIFO start position will not be affected on execution.

Related APIs:: XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit()

◆ XMC_USIC_CH_TXFIFO_SetTriggerLimit()

void XMC_USIC_CH_TXFIFO_SetTriggerLimit	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	limit
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
limit	Threshold for transmit FIFO filling level to be considered for generating events. Range: 0 to fifo size -1.

Returns: None

Description: Sets the trigger limit for the TX FIFO.

Related APIs:: XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit()

◆ XMC_USIC_CH_WriteToTBUF()

void XMC_USIC_CH_WriteToTBUF	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted. Range: 16bit unsigned data. minimum= 0, maximum= 65535

Returns: None

Description: Writes data into the transmit buffer.

The data provided is placed in TBUF[0U].

Related APIs:: XMC_USIC_CH_WriteToTBUFTCI()

◆ XMC_USIC_CH_WriteToTBUFTCI()

void XMC_USIC_CH_WriteToTBUFTCI	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		const uint32_t	transmit_control_information
	)

Parameters

channel	Pointer to USIC channel handler of type XMC_USIC_CH_t Range: XMC_USIC0_CH0, XMC_USIC0_CH1 to XMC_USIC2_CH1 based on device support.
data	Data to be transmitted.
transmit_control_information	transmit control information to be configured while transmitting the data. Range: minimum= 0, maximum= 31.

Returns: None

Description: Writes data to the transmit buffer in a control mode.

When the respective control mode is enabled , this API can be used.

Related APIs:: XMC_USIC_CH_WriteToTBUF()

◆ XMC_USIC_Disable()

void XMC_USIC_Disable ( XMC_USIC_t *const usic )

Parameters

usic	Pointer to USIC module handler of type XMC_USIC_t. Range: XMC_USIC0 to XMC_USIC2 based on device support.

Returns: None

Description: Disables the USIC module.

Disables the clock for the USIC module by following the clock disabling sequence for the selected device.

Related APIs:: XMC_USIC_CH_Disable(), XMC_USIC_Enable()

◆ XMC_USIC_Enable()

void XMC_USIC_Enable ( XMC_USIC_t *const usic )

Parameters

usic	Pointer to USIC module handler of type XMC_USIC_t. Range: XMC_USIC0 to XMC_USIC2 based on device support.

Returns: None

Description: Enables the USIC module.

Enables the clock for the USIC module by following the clock enabling sequence for the selected device.

Related APIs:: XMC_USIC_CH_Enable(), XMC_USIC_Disable()

◆ XMC_USIC_IsChannelValid()

bool XMC_USIC_IsChannelValid ( const XMC_USIC_CH_t *const channel )

< USIC0 channel 0 base address

< USIC0 channel 1 base address

< USIC1 channel 0 base address

< USIC1 channel 1 base address

< USIC2 channel 0 base address

< USIC2 channel 1 base address

◆ XMC_USIC_IsModuleValid()

bool XMC_USIC_IsModuleValid ( const XMC_USIC_t *const module )

< USIC0 module base address

< USIC1 module base address

< USIC2 module base address

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ USIC_CH_DXCR_CM_Msk

◆ USIC_CH_DXCR_CM_Pos

◆ USIC_CH_DXCR_DFEN_Msk

◆ USIC_CH_DXCR_DPOL_Msk

◆ USIC_CH_DXCR_DSEL_Msk

◆ USIC_CH_DXCR_DSEL_Pos

◆ USIC_CH_DXCR_DSEN_Msk

◆ USIC_CH_DXCR_INSW_Msk

◆ USIC_CH_DXCR_INSW_pos

◆ USIC_CH_DXCR_SFSEL_Msk

◆ USIC_CH_DXCR_SFSEL_Pos

◆ XMC_USIC0

◆ XMC_USIC0_CH0

◆ XMC_USIC0_CH1

◆ XMC_USIC1

◆ XMC_USIC1_CH0

◆ XMC_USIC1_CH1

◆ XMC_USIC2

◆ XMC_USIC2_CH0

◆ XMC_USIC2_CH1

Typedef Documentation

◆ XMC_USIC_t

Enumeration Type Documentation

◆ XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t

◆ XMC_USIC_CH_BRG_CLOCK_SOURCE_t

◆ XMC_USIC_CH_BRG_CTQSEL_t

◆ XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t

◆ XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t

◆ XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t

◆ XMC_USIC_CH_DATA_OUTPUT_MODE_t

◆ XMC_USIC_CH_EVENT_t

◆ XMC_USIC_CH_FIFO_SIZE_t

◆ XMC_USIC_CH_INPUT_COMBINATION_MODE_t

◆ XMC_USIC_CH_INPUT_SAMPLING_FREQ_t

◆ XMC_USIC_CH_INPUT_t

◆ XMC_USIC_CH_INTERRUPT_NODE_POINTER_t

◆ XMC_USIC_CH_KERNEL_MODE_t

◆ XMC_USIC_CH_OPERATING_MODE_t

◆ XMC_USIC_CH_PARITY_MODE_t

◆ XMC_USIC_CH_PASSIVE_DATA_LEVEL_t

◆ XMC_USIC_CH_RBUF_STATUS_t

◆ XMC_USIC_CH_RXFIFO_EVENT_CONF_t

◆ XMC_USIC_CH_RXFIFO_EVENT_t

◆ XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t

◆ XMC_USIC_CH_SHIFT_DIRECTION_t

◆ XMC_USIC_CH_START_TRANSMISION_MODE_t

◆ XMC_USIC_CH_STATUS_t

◆ XMC_USIC_CH_TBUF_STATUS_SET_t

◆ XMC_USIC_CH_TBUF_STATUS_t

◆ XMC_USIC_CH_TXFIFO_EVENT_CONF_t

◆ XMC_USIC_CH_TXFIFO_EVENT_t

◆ XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t

Function Documentation

◆ XMC_USIC_CH_ConfigExternalInputSignalToBRG()

◆ XMC_USIC_CH_ConfigureShiftClockOutput()

◆ XMC_USIC_CH_ConnectInputDataShiftToDataInput()

◆ XMC_USIC_CH_ConnectInputDataShiftToPPP()

◆ XMC_USIC_CH_Disable()

◆ XMC_USIC_CH_DisableDelayCompensation()

◆ XMC_USIC_CH_DisableEvent()

◆ XMC_USIC_CH_DisableFrameLengthControl()

◆ XMC_USIC_CH_DisableInputDigitalFilter()

◆ XMC_USIC_CH_DisableInputInversion()

◆ XMC_USIC_CH_DisableInputSync()

◆ XMC_USIC_CH_DisableTBUFDataValidTrigger()

◆ XMC_USIC_CH_DisableTimeMeasurement()

◆ XMC_USIC_CH_DisableWordLengthControl()

◆ XMC_USIC_CH_Enable()

◆ XMC_USIC_CH_EnableDelayCompensation()

◆ XMC_USIC_CH_EnableEvent()

◆ XMC_USIC_CH_EnableFrameLengthControl()

◆ XMC_USIC_CH_EnableInputDigitalFilter()

◆ XMC_USIC_CH_EnableInputInversion()