Data Structures
struct	XMC_SCU_CLOCK_CONFIG_t

struct	XMC_SCU_SUPPLYMONITOR_t

Macros
#define	XMC_BMI_ADDR (0x10000e00U)

#define	XMC_SCU_BMI_CANCLK_DCO1 (0U << 11)

#define	XMC_SCU_BMI_CANCLK_OSCHP (1U << 11)

#define	XMC_SCU_BMI_DAPDIS_CHANNEL_0 (0U << 9)

#define	XMC_SCU_BMI_DAPDIS_CHANNEL_1 (1U << 9)

#define	XMC_SCU_BMI_DAPTYP_SPD (1U << 8)

#define	XMC_SCU_BMI_DAPTYP_SWD (0U << 8)

#define	XMC_SCU_BMI_HWCFG_ASC_BSL (0x0040U)

#define	XMC_SCU_BMI_HWCFG_ASC_BSLTO (0x0050U)

#define	XMC_SCU_BMI_HWCFG_CAN_BSL (0x0000U)

#define	XMC_SCU_BMI_HWCFG_CAN_BSLTO (0x0010U)

#define	XMC_SCU_BMI_HWCFG_PINDIS (0x0080U)

#define	XMC_SCU_BMI_HWCFG_SBSL (0x007AU)

#define	XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (0x0020U)

#define	XMC_SCU_BMI_HWCFG_SSC_BSL (0x0048U)

#define	XMC_SCU_BMI_HWCFG_SSC_BSLTO (0x0058U)

#define	XMC_SCU_BMI_HWCFG_UMD (0x0043U)

#define	XMC_SCU_BMI_HWCFG_UMHAR (0x0047U)

#define	XMC_SCU_BMI_HWCFG_UPM (0x0041U)

#define	XMC_SCU_INTERRUPT_EVENT_ACMP0 SCU_INTERRUPT_SRMSK_ACMP0I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ACMP1 SCU_INTERRUPT_SRMSK_ACMP1I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ACMP2 SCU_INTERRUPT_SRMSK_ACMP2I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ACMP3 (((int64_t)SCU_INTERRUPT_SRMSK1_ACMP3I_Msk) << 32U)

#define	XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC (((int64_t)SCU_INTERRUPT_SRMSK1_DCO1OFSI_Msk) << 32U)

#define	XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR SCU_INTERRUPT_SRMSK_FLECC2I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_LOCI SCU_INTERRUPT_SRMSK_LOCI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK (((int64_t)SCU_INTERRUPT_SRMSK1_LOECI_Msk) << 32U)

#define	XMC_SCU_INTERRUPT_EVENT_ORC0 SCU_INTERRUPT_SRMSK_ORC0I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC1 SCU_INTERRUPT_SRMSK_ORC1I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC2 SCU_INTERRUPT_SRMSK_ORC2I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC3 SCU_INTERRUPT_SRMSK_ORC3I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC4 SCU_INTERRUPT_SRMSK_ORC4I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC5 SCU_INTERRUPT_SRMSK_ORC5I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC6 SCU_INTERRUPT_SRMSK_ORC6I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_ORC7 SCU_INTERRUPT_SRMSK_ORC7I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_PEMCAN (((int64_t)SCU_INTERRUPT_SRMSK1_PEMCI_Msk) << 32U)

#define	XMC_SCU_INTERRUPT_EVENT_PESRAM SCU_INTERRUPT_SRMSK_PESRAMI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_PEUSIC0 SCU_INTERRUPT_SRMSK_PEU0I_Msk

#define	XMC_SCU_INTERRUPT_EVENT_PEUSIC1 (((int64_t)SCU_INTERRUPT_SRMSK1_PEU1I_Msk) << 32U)

#define	XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRCLR_AI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRCLR_PI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRMSK_RTC_CTR_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk

#define	XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk

#define	XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_TSE_DONE SCU_INTERRUPT_SRMSK_TSE_DONE_Msk

#define	XMC_SCU_INTERRUPT_EVENT_TSE_HIGH SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk

#define	XMC_SCU_INTERRUPT_EVENT_TSE_LOW SCU_INTERRUPT_SRMSK_TSE_LOW_Msk

#define	XMC_SCU_INTERRUPT_EVENT_VCLIP SCU_INTERRUPT_SRMSK_VCLIPI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_VDDPI SCU_INTERRUPT_SRMSK_VDDPI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_VDROP SCU_INTERRUPT_SRMSK_VDROPI_Msk

#define	XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRMSK_PRWARN_Msk

Typedefs
typedef void(*	XMC_SCU_INTERRUPT_EVENT_HANDLER_t) (void)

typedef uint32_t	XMC_SCU_INTERRUPT_EVENT_t

Enumerations
enum	XMC_SCU_CCU_TRIGGER_t

enum	XMC_SCU_CLOCK_ADCCLKSRC_t

enum	XMC_SCU_CLOCK_DCLKSRC_t

enum	XMC_SCU_CLOCK_OSCHP_MODE_t

enum	XMC_SCU_CLOCK_OSCLP_MODE_t

enum	XMC_SCU_CLOCK_PCLKSRC_t

enum	XMC_SCU_CLOCK_RTCCLKSRC_t

enum	XMC_SCU_CLOCK_SYNC_CLKSRC_t

enum	XMC_SCU_IRQCTRL_t

enum	XMC_SCU_PERIPHERAL_CLOCK_t

enum	XMC_SCU_POWER_MONITOR_DELAY_t

enum	XMC_SCU_POWER_MONITOR_RANGE_t

enum	XMC_SCU_RESET_REASON_t

enum	XMC_SCU_STATUS_t

enum	XMC_SCU_SYSTEM_RESET_REQUEST_t

Functions
uint32_t	XMC_SCU_CalcTemperature (void)

void	XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature (int32_t temperature)

void	XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus (void)

void	XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration (void)

void	XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog (void)

void	XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration (XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_clk, uint32_t prescaler, uint32_t syn_preload)

void	XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog (void)

void	XMC_SCU_CLOCK_GatePeripheralClock (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)

uint32_t	XMC_SCU_CLOCK_GetCpuClockFrequency (void)

uint32_t	XMC_SCU_CLOCK_GetFastPeripheralClockFrequency (void)

uint32_t	XMC_SCU_CLOCK_GetPeripheralClockFrequency (void)

void	XMC_SCU_CLOCK_Init (const XMC_SCU_CLOCK_CONFIG_t *const config)

bool	XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady (void)

bool	XMC_SCU_CLOCK_IsPeripheralClockGated (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)

void	XMC_SCU_CLOCK_ScaleMCLKFrequency (uint32_t idiv, uint32_t fdiv)

void	XMC_SCU_CLOCK_SetAdcClockSrc (XMC_SCU_CLOCK_ADCCLKSRC_t adcclk_src)

void	XMC_SCU_CLOCK_SetFastPeripheralClockSource (const XMC_SCU_CLOCK_PCLKSRC_t source)

void	XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode (XMC_SCU_CLOCK_OSCHP_MODE_t mode)

void	XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode (XMC_SCU_CLOCK_OSCLP_MODE_t mode)

void	XMC_SCU_CLOCK_SetMCLKFrequency (uint32_t freq_khz)

void	XMC_SCU_CLOCK_UngatePeripheralClock (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)

void	XMC_SCU_DisablePrefetchUnit (void)

void	XMC_SCU_EnablePrefetchUnit (void)

uint32_t	XMC_SCU_GetBMI (void)

uint32_t	XMC_SCU_GetMirrorStatus (void)

uint32_t	XMC_SCU_GetTemperature (void)

bool	XMC_SCU_HighTemperature (void)

void	XMC_SCU_INTERRUPT_ClearEventStatus (const XMC_SCU_INTERRUPT_EVENT_t event)

void	XMC_SCU_INTERRUPT_DisableEvent (const XMC_SCU_INTERRUPT_EVENT_t event)

void	XMC_SCU_INTERRUPT_EnableEvent (const XMC_SCU_INTERRUPT_EVENT_t event)

XMC_SCU_STATUS_t	XMC_SCU_INTERRUPT_SetEventHandler (const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler)

void	XMC_SCU_INTERRUPT_TriggerEvent (const XMC_SCU_INTERRUPT_EVENT_t event)

XMC_SCU_INTERRUPT_EVENT_t	XMC_SCU_INTERUPT_GetEventStatus (void)

void	XMC_SCU_IRQHandler (uint32_t sr_num)

bool	XMC_SCU_IsTempMeasurementDone (void)

void	XMC_SCU_LockProtectedBits (void)

bool	XMC_SCU_LowTemperature (void)

void	XMC_SCU_POWER_DisableMonitor (void)

void	XMC_SCU_POWER_EnableMonitor (XMC_SCU_POWER_MONITOR_RANGE_t range, XMC_SCU_POWER_MONITOR_DELAY_t delay)

void	XMC_SCU_RESET_AssertMasterReset (void)

void	XMC_SCU_RESET_ClearDeviceResetReason (void)

void	XMC_SCU_RESET_EnableResetRequest (uint32_t request)

uint32_t	XMC_SCU_RESET_GetDeviceResetReason (void)

uint32_t	XMC_SCU_SetBMI (uint32_t flags, uint8_t timeout)

void	XMC_SCU_SetCcuTriggerHigh (const uint32_t trigger)

void	XMC_SCU_SetCcuTriggerLow (const uint32_t trigger)

void	XMC_SCU_SetInterruptControl (uint8_t irq_number, XMC_SCU_IRQCTRL_t source)

void	XMC_SCU_SetRawTempLimits (const uint32_t lower_temp, const uint32_t upper_temp)

XMC_SCU_STATUS_t	XMC_SCU_SetTempHighLimit (uint32_t limit)

XMC_SCU_STATUS_t	XMC_SCU_SetTempLowLimit (uint32_t limit)

void	XMC_SCU_StartTempMeasurement (void)

void	XMC_SCU_StopTempMeasurement (void)

void	XMC_SCU_SupplyMonitorInit (const XMC_SCU_SUPPLYMONITOR_t *obj)

void	XMC_SCU_UnlockProtectedBits (void)

Detailed Description

System control unit is the SoC power, reset and a clock manager with additional responsibility of providing system stability protection and other auxiliary functions.
SCU provides the following features,

Power control
Reset control
Clock control
Miscellaneous control(boot mode, system interrupts etc.)

The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic and miscellaneous control logic.

Clock driver features:

Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init()
Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()
Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()

Reset driver features:

Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()
Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest()

Interrupt driver features:

Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), XMC_SCU_INTERRUPT_DisableEvent()
Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()

Miscellaneous features:

Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh()
Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()
Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()
Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()

Macro Definition Documentation

◆ XMC_BMI_ADDR

#define XMC_BMI_ADDR (0x10000e00U)

Boot Mode Index (BMI) address holding information about start-up mode and debug configuration of the device.

◆ XMC_SCU_BMI_CANCLK_DCO1

#define XMC_SCU_BMI_CANCLK_DCO1 (0U << 11)

Synchronous CAN clock via internal oscillator (DCO1) with enabled trimming via external reference is selected

◆ XMC_SCU_BMI_CANCLK_OSCHP

#define XMC_SCU_BMI_CANCLK_OSCHP (1U << 11)

Synchronous CAN clock via external oscillator (OSC_HP) is selected

◆ XMC_SCU_BMI_DAPDIS_CHANNEL_0

#define XMC_SCU_BMI_DAPDIS_CHANNEL_0 (0U << 9)

SWD/SPD_0 pin is selected

◆ XMC_SCU_BMI_DAPDIS_CHANNEL_1

#define XMC_SCU_BMI_DAPDIS_CHANNEL_1 (1U << 9)

SWD/SPD_1 pin is selected

◆ XMC_SCU_BMI_DAPTYP_SPD

#define XMC_SCU_BMI_DAPTYP_SPD (1U << 8)

Single pin debug (SPD) interface is selected

◆ XMC_SCU_BMI_DAPTYP_SWD

#define XMC_SCU_BMI_DAPTYP_SWD (0U << 8)

Serial wire debug (SWD) interface is selected

◆ XMC_SCU_BMI_HWCFG_ASC_BSL

#define XMC_SCU_BMI_HWCFG_ASC_BSL (0x0040U)

ASC Bootstrap Loader Start-up Mode

◆ XMC_SCU_BMI_HWCFG_ASC_BSLTO

#define XMC_SCU_BMI_HWCFG_ASC_BSLTO (0x0050U)

ASC BSL Start-up Mode with time-out

◆ XMC_SCU_BMI_HWCFG_CAN_BSL

#define XMC_SCU_BMI_HWCFG_CAN_BSL (0x0000U)

CAN Bootstrap Loader Start-up Mode

◆ XMC_SCU_BMI_HWCFG_CAN_BSLTO

#define XMC_SCU_BMI_HWCFG_CAN_BSLTO (0x0010U)

CAN Bootstrap Loader Start-up Mode with time-out

◆ XMC_SCU_BMI_HWCFG_PINDIS

#define XMC_SCU_BMI_HWCFG_PINDIS (0x0080U)

Boot Configuration Type Selection, Boot from BMI is selected

◆ XMC_SCU_BMI_HWCFG_SBSL

#define XMC_SCU_BMI_HWCFG_SBSL (0x007AU)

Secure Bootstrap Loader Start-up Mode over ASC

◆ XMC_SCU_BMI_HWCFG_SBSL_CANOPEN

#define XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (0x0020U)

Secure Bootstrap Loader Start-up Mode over CANopen

◆ XMC_SCU_BMI_HWCFG_SSC_BSL

#define XMC_SCU_BMI_HWCFG_SSC_BSL (0x0048U)

SSC Bootstrap Loader Start-up Mode

◆ XMC_SCU_BMI_HWCFG_SSC_BSLTO

#define XMC_SCU_BMI_HWCFG_SSC_BSLTO (0x0058U)

SSC BSL Start-up Mode with time-out

◆ XMC_SCU_BMI_HWCFG_UMD

#define XMC_SCU_BMI_HWCFG_UMD (0x0043U)

User Start-up Mode with debug enabled

◆ XMC_SCU_BMI_HWCFG_UMHAR

#define XMC_SCU_BMI_HWCFG_UMHAR (0x0047U)

User Start-up Mode with debug enabled and halt after reset (HAR)

◆ XMC_SCU_BMI_HWCFG_UPM

#define XMC_SCU_BMI_HWCFG_UPM (0x0041U)

User productive Start-up Mode

◆ XMC_SCU_INTERRUPT_EVENT_ACMP0

#define XMC_SCU_INTERRUPT_EVENT_ACMP0 SCU_INTERRUPT_SRMSK_ACMP0I_Msk

Analog comparator-0 output event.

◆ XMC_SCU_INTERRUPT_EVENT_ACMP1

#define XMC_SCU_INTERRUPT_EVENT_ACMP1 SCU_INTERRUPT_SRMSK_ACMP1I_Msk

Analog comparator-1 output event.

◆ XMC_SCU_INTERRUPT_EVENT_ACMP2

#define XMC_SCU_INTERRUPT_EVENT_ACMP2 SCU_INTERRUPT_SRMSK_ACMP2I_Msk

Analog comparator-2 output event.

◆ XMC_SCU_INTERRUPT_EVENT_ACMP3

#define XMC_SCU_INTERRUPT_EVENT_ACMP3 (((int64_t)SCU_INTERRUPT_SRMSK1_ACMP3I_Msk) << 32U)

Analog comparator-3 output event.

Note: Only available for XMC1400 series

◆ XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC

#define XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC (((int64_t)SCU_INTERRUPT_SRMSK1_DCO1OFSI_Msk) << 32U)

DCO1 Out of SYNC Event.

Note: Only available for XMC1400 series

◆ XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED

#define XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk

Flash operation completion event.

◆ XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR

#define XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR SCU_INTERRUPT_SRMSK_FLECC2I_Msk

Flash ECC double bit error event.

◆ XMC_SCU_INTERRUPT_EVENT_LOCI

#define XMC_SCU_INTERRUPT_EVENT_LOCI SCU_INTERRUPT_SRMSK_LOCI_Msk

Loss of clock event.

◆ XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK

#define XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK (((int64_t)SCU_INTERRUPT_SRMSK1_LOECI_Msk) << 32U)

Loss of external OSC_HP clock event.

Note: Only available for XMC1400 series

◆ XMC_SCU_INTERRUPT_EVENT_ORC0

#define XMC_SCU_INTERRUPT_EVENT_ORC0 SCU_INTERRUPT_SRMSK_ORC0I_Msk

Out of range comparator-0 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC1

#define XMC_SCU_INTERRUPT_EVENT_ORC1 SCU_INTERRUPT_SRMSK_ORC1I_Msk

Out of range comparator-1 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC2

#define XMC_SCU_INTERRUPT_EVENT_ORC2 SCU_INTERRUPT_SRMSK_ORC2I_Msk

Out of range comparator-2 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC3

#define XMC_SCU_INTERRUPT_EVENT_ORC3 SCU_INTERRUPT_SRMSK_ORC3I_Msk

Out of range comparator-3 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC4

#define XMC_SCU_INTERRUPT_EVENT_ORC4 SCU_INTERRUPT_SRMSK_ORC4I_Msk

Out of range comparator-4 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC5

#define XMC_SCU_INTERRUPT_EVENT_ORC5 SCU_INTERRUPT_SRMSK_ORC5I_Msk

Out of range comparator-5 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC6

#define XMC_SCU_INTERRUPT_EVENT_ORC6 SCU_INTERRUPT_SRMSK_ORC6I_Msk

Out of range comparator-6 event.

◆ XMC_SCU_INTERRUPT_EVENT_ORC7

#define XMC_SCU_INTERRUPT_EVENT_ORC7 SCU_INTERRUPT_SRMSK_ORC7I_Msk

Out of range comparator-7 event.

◆ XMC_SCU_INTERRUPT_EVENT_PEMCAN

#define XMC_SCU_INTERRUPT_EVENT_PEMCAN (((int64_t)SCU_INTERRUPT_SRMSK1_PEMCI_Msk) << 32U)

MultiCAN SRAM Parity Error Event.

◆ XMC_SCU_INTERRUPT_EVENT_PESRAM

#define XMC_SCU_INTERRUPT_EVENT_PESRAM SCU_INTERRUPT_SRMSK_PESRAMI_Msk

PSRAM Parity error event.

◆ XMC_SCU_INTERRUPT_EVENT_PEUSIC0

#define XMC_SCU_INTERRUPT_EVENT_PEUSIC0 SCU_INTERRUPT_SRMSK_PEU0I_Msk

USIC0 Parity error event.

◆ XMC_SCU_INTERRUPT_EVENT_PEUSIC1

#define XMC_SCU_INTERRUPT_EVENT_PEUSIC1 (((int64_t)SCU_INTERRUPT_SRMSK1_PEU1I_Msk) << 32U)

USIC1 Parity error event.

◆ XMC_SCU_INTERRUPT_EVENT_RTC_ALARM

#define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRCLR_AI_Msk

RTC alarm event.

◆ XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC

#define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRCLR_PI_Msk

RTC periodic event.

◆ XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED

#define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk

RTCATIM0 register update event.

◆ XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED

#define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk

RTCATIM1 register update event.

◆ XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED

#define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRMSK_RTC_CTR_Msk

RTCCTR register update event.

◆ XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED

#define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk

RTCTIM0 register update event.

◆ XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED

#define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk

RTCTIM1 register update event.

◆ XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL

#define XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk

Standby clock failure event.

◆ XMC_SCU_INTERRUPT_EVENT_TSE_DONE

#define XMC_SCU_INTERRUPT_EVENT_TSE_DONE SCU_INTERRUPT_SRMSK_TSE_DONE_Msk

Temperature measurement Completion event.

◆ XMC_SCU_INTERRUPT_EVENT_TSE_HIGH

#define XMC_SCU_INTERRUPT_EVENT_TSE_HIGH SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk

Temperature too high event.

◆ XMC_SCU_INTERRUPT_EVENT_TSE_LOW

#define XMC_SCU_INTERRUPT_EVENT_TSE_LOW SCU_INTERRUPT_SRMSK_TSE_LOW_Msk

Temperature too low event.

◆ XMC_SCU_INTERRUPT_EVENT_VCLIP

#define XMC_SCU_INTERRUPT_EVENT_VCLIP SCU_INTERRUPT_SRMSK_VCLIPI_Msk

VCLIP event.

◆ XMC_SCU_INTERRUPT_EVENT_VDDPI

#define XMC_SCU_INTERRUPT_EVENT_VDDPI SCU_INTERRUPT_SRMSK_VDDPI_Msk

VDDP pre-warning event.

◆ XMC_SCU_INTERRUPT_EVENT_VDROP

#define XMC_SCU_INTERRUPT_EVENT_VDROP SCU_INTERRUPT_SRMSK_VDROPI_Msk

VDROP event.

◆ XMC_SCU_INTERRUPT_EVENT_WDT_WARN

#define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRMSK_PRWARN_Msk

WDT pre-warning event.

Typedef Documentation

◆ XMC_SCU_INTERRUPT_EVENT_HANDLER_t

typedef void(* XMC_SCU_INTERRUPT_EVENT_HANDLER_t) (void)

Function pointer type used for registering callback functions on SCU event occurrence.

◆ XMC_SCU_INTERRUPT_EVENT_t

typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t

Defines list of events that can generate SCU interrupt. These enums can be used to configure events in SRMSK register for assertion of interrupt. All the enum items are tabulated as per bits present in SRMSK register. Use type XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. These enums can also be used for checking the status of events from the SRSTAT register.

Enumeration Type Documentation

◆ XMC_SCU_CCU_TRIGGER_t

enum XMC_SCU_CCU_TRIGGER_t

Defines options for Capture/Compare unit timer slice trigger that enables synchronous start function available on the SCU, CCUCON register. Use type XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters.

Enumerator
XMC_SCU_CCU_TRIGGER_CCU40	Trigger CCU40 peripheral.
XMC_SCU_CCU_TRIGGER_CCU80	Trigger CCU80 peripheral.
XMC_SCU_CCU_TRIGGER_CCU41	Trigger CCU40 peripheral.
XMC_SCU_CCU_TRIGGER_CCU81	Trigger CCU80 peripheral.

◆ XMC_SCU_CLOCK_ADCCLKSRC_t

enum XMC_SCU_CLOCK_ADCCLKSRC_t

ADC clock source selection

Note: Only available in XMC1400 series

Enumerator
XMC_SCU_CLOCK_ADCCLKSRC_48MHZ	Internal oscillator DCO1 (48MHz)
XMC_SCU_CLOCK_ADCCLKSRC_32MHZ	Internal oscillator DCO1 (48MHz) divided by 1.5

◆ XMC_SCU_CLOCK_DCLKSRC_t

enum XMC_SCU_CLOCK_DCLKSRC_t

DCLK clock source selection

Note: Only available in XMC1400 series

Enumerator
XMC_SCU_CLOCK_DCLKSRC_DCO1	Internal oscillator DCO1 (48MHz)
XMC_SCU_CLOCK_DCLKSRC_EXT_XTAL	External crystal oscillator

◆ XMC_SCU_CLOCK_OSCHP_MODE_t

enum XMC_SCU_CLOCK_OSCHP_MODE_t

OSCHP mode

Note: Only available in XMC1400 series

Enumerator
XMC_SCU_CLOCK_OSCHP_MODE_OSC	Oscillator is enabled and in active power mode with shaper enabled
XMC_SCU_CLOCK_OSCHP_MODE_DIRECT	Oscillator in power down mode with shaper enabled
XMC_SCU_CLOCK_OSCHP_MODE_DISABLED	Oscillator in power down mode with shaper enabled

◆ XMC_SCU_CLOCK_OSCLP_MODE_t

enum XMC_SCU_CLOCK_OSCLP_MODE_t

OSCLP mode

Note: Only available in XMC1400 series

Enumerator
XMC_SCU_CLOCK_OSCLP_MODE_OSC	Oscillator is enabled and in active power mode with shaper enabled
XMC_SCU_CLOCK_OSCLP_MODE_DISABLED	Oscillator in power down mode with shaper enabled

◆ XMC_SCU_CLOCK_PCLKSRC_t

enum XMC_SCU_CLOCK_PCLKSRC_t

Defines possible sources of peripheral clock (PCLK). These enums can be used to configure PCLKSEL bits of CLKCR Clock Control Register. Use type XMC_SCU_CLOCK_PCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_PCLKSRC_MCLK	MCLK as the source for PCLK.
XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK	Source of PCLK is twice the MCLK.

◆ XMC_SCU_CLOCK_RTCCLKSRC_t

enum XMC_SCU_CLOCK_RTCCLKSRC_t

Defines possible sources of RTC clock. These enums can be used to configure RTCCLKSEL bits of CLKCR Clock Control Register. Use type XMC_SCU_CLOCK_RTCCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_RTCCLKSRC_DCO2	RTC clock source is standby clock.
XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0	RTC clock source is external clock from ERU0.IOUT0.
XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT	RTC clock source is external clock from ACMP0.OUT.
XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT	RTC clock source is external clock from ACMP1.OUT.
XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT	RTC clock source is external clock from ACMP2.OUT.
XMC_SCU_CLOCK_RTCCLKSRC_OSCLP	32.768kHz XTAL clock via OSC_LP. Note Only available for XMC1400 series

◆ XMC_SCU_CLOCK_SYNC_CLKSRC_t

enum XMC_SCU_CLOCK_SYNC_CLKSRC_t

Clock source for synchronization

Note: Only available in XMC1400 series

◆ XMC_SCU_IRQCTRL_t

enum XMC_SCU_IRQCTRL_t

Selects the service request connected to the interrupt node.

Note: Only available for XMC1400 series

Enumerator
XMC_SCU_IRQCTRL_SCU_SR0_IRQ0	SCU_SR0 connected to IRQ0
XMC_SCU_IRQCTRL_CAN0_SR0_IRQ0	CAN0_SR0 connected to IRQ0
XMC_SCU_IRQCTRL_CCU40_SR0_IRQ0	CCU40_SR0 connected to IRQ0
XMC_SCU_IRQCTRL_SCU_SR0_OR_CAN0_SR0_IRQ0	SCU_SR0 and CAN_SR0 are both connected to IRQ0
XMC_SCU_IRQCTRL_SCU_SR1_IRQ1	SCU_SR1 connected to IRQ1
XMC_SCU_IRQCTRL_CAN0_SR1_IRQ1	CAN0_SR1 connected to IRQ1
XMC_SCU_IRQCTRL_CCU80_SR0_IRQ1	CCU80_SR0 connected to IRQ1
XMC_SCU_IRQCTRL_SCU_SR1_OR_CAN0_SR1_IRQ1	SCU_SR1 and CAN0_SR1 connected to IRQ1
XMC_SCU_IRQCTRL_SCU_SR2_IRQ2	SCU_SR2 connected to IRQ2
XMC_SCU_IRQCTRL_CAN0_SR2_IRQ2	CAN0_SR2 connected to IRQ2
XMC_SCU_IRQCTRL_CCU80_SR1_IRQ2	CCU80_SR1 connected to IRQ2
XMC_SCU_IRQCTRL_SCU_SR2_OR_CAN0_SR2_IRQ2	SCU_SR2 and CAN0_SR2 connected to IRQ2
XMC_SCU_IRQCTRL_ERU0_SR0_IRQ3	ERU0_SR0 connected to IRQ3
XMC_SCU_IRQCTRL_ERU1_SR0_IRQ3	ERU1_SR0 connected to IRQ3
XMC_SCU_IRQCTRL_CAN0_SR0_IRQ3	CAN0_SR0 connected to IRQ3
XMC_SCU_IRQCTRL_ERU0_SR0_OR_ERU1_SR0_IRQ3	ERU0_SR0 and ERU1_SR0 connected to IRQ3
XMC_SCU_IRQCTRL_ERU0_SR1_IRQ4	ERU0_SR1 connected to IRQ4
XMC_SCU_IRQCTRL_ERU1_SR1_IRQ4	ERU1_SR1 connected to IRQ4
XMC_SCU_IRQCTRL_CAN0_SR1_IRQ4	CAN0_SR1 connected to IRQ4
XMC_SCU_IRQCTRL_ERU0_SR1_OR_ERU1_SR1_IRQ4	ERU0_SR1 and ERU1_SR1 connected to IRQ4
XMC_SCU_IRQCTRL_ERU0_SR2_IRQ5	ERU0_SR2 connected to IRQ5
XMC_SCU_IRQCTRL_ERU1_SR2_IRQ5	ERU1_SR2 connected to IRQ5
XMC_SCU_IRQCTRL_CAN0_SR2_IRQ5	CAN0_SR2 connected to IRQ5
XMC_SCU_IRQCTRL_ERU0_SR2_OR_ERU1_SR2_IRQ5	ERU0_SR2 and ERU1_SR2 connected to IRQ5
XMC_SCU_IRQCTRL_ERU0_SR3_IRQ6	ERU0_SR3 connected to IRQ6
XMC_SCU_IRQCTRL_ERU1_SR3_IRQ6	ERU1_SR3 connected to IRQ6
XMC_SCU_IRQCTRL_CAN0_SR3_IRQ6	CAN0_SR3 connected to IRQ6
XMC_SCU_IRQCTRL_ERU0_SR3_OR_ERU1_SR3_IRQ6	ERU0_SR3 and ERU1_SR3 connected to IRQ6
XMC_SCU_IRQCTRL_MATH_SR0_IRQ7	MATH_SR0 connected to IRQ7
XMC_SCU_IRQCTRL_CAN0_SR3_IRQ7	CAN0_SR3 connected to IRQ7
XMC_SCU_IRQCTRL_CCU40_SR1_IRQ7	CCU40_SR1 connected to IRQ7
XMC_SCU_IRQCTRL_MATH_SR0_OR_CAN0_SR3_IRQ7	MATH_SR0 and CAN0_SR3 connected to IRQ7
XMC_SCU_IRQCTRL_LEDTS2_SR0_IRQ8	LEDTS2_SR0 connected to IRQ8
XMC_SCU_IRQCTRL_CCU40_SR0_IRQ8	CCU40_SR0 connected to IRQ8
XMC_SCU_IRQCTRL_CCU80_SR0_IRQ8	CCU80_SR0 connected to IRQ8
XMC_SCU_IRQCTRL_LEDTS2_SR0_OR_CCU40_SR0_IRQ8	LEDTS2_SR0 and CCU40_SR0 connected to IRQ8
XMC_SCU_IRQCTRL_USIC0_SR0_IRQ9	USIC0_SR0 connected to IRQ9
XMC_SCU_IRQCTRL_USIC1_SR0_IRQ9	USIC1_SR0 connected to IRQ9
XMC_SCU_IRQCTRL_ERU0_SR0_IRQ9	ERU0_SR0 connected to IRQ9
XMC_SCU_IRQCTRL_USIC0_SR0_OR_USIC1_SR0_IRQ9	USIC0_SR0 and USIC1_SR0 connected to IRQ9
XMC_SCU_IRQCTRL_USIC0_SR1_IRQ10	USIC0_SR1 connected to IRQ10
XMC_SCU_IRQCTRL_USIC1_SR1_IRQ10	USIC1_SR1 connected to IRQ10
XMC_SCU_IRQCTRL_ERU0_SR1_IRQ10	ERU0_SR1 connected to IRQ10
XMC_SCU_IRQCTRL_USIC0_SR1_OR_USIC1_SR1_IRQ10	USIC0_SR1 and USIC1_SR1 connected to IRQ10
XMC_SCU_IRQCTRL_USIC0_SR2_IRQ11	USIC0_SR2 connected to IRQ11
XMC_SCU_IRQCTRL_USIC1_SR2_IRQ11	USIC1_SR2 connected to IRQ11
XMC_SCU_IRQCTRL_ERU0_SR2_IRQ11	ERU0_SR2 connected to IRQ11
XMC_SCU_IRQCTRL_USIC0_SR2_OR_USIC1_SR2_IRQ11	USIC0_SR2 and USIC1_SR2 connected to IRQ11
XMC_SCU_IRQCTRL_USIC0_SR3_IRQ12	USIC0_SR3 connected to IRQ12
XMC_SCU_IRQCTRL_USIC1_SR3_IRQ12	USIC1_SR3 connected to IRQ12
XMC_SCU_IRQCTRL_ERU0_SR3_IRQ12	ERU0_SR3 connected to IRQ12
XMC_SCU_IRQCTRL_USIC0_SR3_OR_USIC1_SR3_IRQ12	USIC0_SR3 and USIC1_SR3 connected to IRQ12
XMC_SCU_IRQCTRL_USIC0_SR4_IRQ13	USIC0_SR4 connected to IRQ13
XMC_SCU_IRQCTRL_USIC1_SR4_IRQ13	USIC1_SR4 connected to IRQ13
XMC_SCU_IRQCTRL_CCU80_SR1_IRQ13	CCU80_SR1 connected to IRQ13
XMC_SCU_IRQCTRL_USIC0_SR4_OR_USIC1_SR4_IRQ13	USIC0_SR4 and USIC1_SR4 connected to IRQ13
XMC_SCU_IRQCTRL_USIC0_SR5_IRQ14	USIC0_SR5 connected to IRQ14
XMC_SCU_IRQCTRL_USIC1_SR5_IRQ14	USIC1_SR5 connected to IRQ14
XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ14	POSIF0_SR0 connected to IRQ14
XMC_SCU_IRQCTRL_USIC0_SR5_OR_USIC1_SR5_IRQ14	USIC0_SR5 and USIC1_SR5 connected to IRQ14
XMC_SCU_IRQCTRL_VADC0_C0SR0_IRQ15	VADC0_C0SR0 connected to IRQ15
XMC_SCU_IRQCTRL_USIC0_SR0_IRQ15	USIC0_SR0 connected to IRQ15
XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ15	POSIF0_SR1 connected to IRQ15
XMC_SCU_IRQCTRL_VADC0_C0SR0_OR_USIC0_SR0_IRQ15	VADC0_C0SR0 and USIC0_SR0 connected to IRQ15
XMC_SCU_IRQCTRL_VADC0_C0SR1_IRQ16	VADC0_C0SR1 connected to IRQ16
XMC_SCU_IRQCTRL_USIC0_SR1_IRQ16	USIC0_SR1 connected to IRQ16
XMC_SCU_IRQCTRL_CCU40_SR2_IRQ16	CCU40_SR2 connected to IRQ16
XMC_SCU_IRQCTRL_VADC0_C0SR1_OR_USIC0_SR1_IRQ16	VADC0_C0SR1 and USIC0_SR1 connected to IRQ16
XMC_SCU_IRQCTRL_VADC0_G0SR0_IRQ17	VADC0_G0SR0 connected to IRQ17
XMC_SCU_IRQCTRL_USIC0_SR2_IRQ17	USIC0_SR2 connected to IRQ17
XMC_SCU_IRQCTRL_CAN0_SR0_IRQ17	CAN0_SR0 connected to IRQ17
XMC_SCU_IRQCTRL_VADC0_G0SR0_OR_USIC0_SR2_IRQ17	VADC0_G0SR0 and USIC0_SR2 connected to IRQ17
XMC_SCU_IRQCTRL_VADC0_G0SR1_IRQ18	VADC0_G0SR1 connected to IRQ18
XMC_SCU_IRQCTRL_USIC0_SR3_IRQ18	USIC0_SR3 connected to IRQ18
XMC_SCU_IRQCTRL_CAN0_SR1_IRQ18	CAN0_SR1 connected to IRQ18
XMC_SCU_IRQCTRL_VADC0_G0SR1_OR_USIC0_SR3_IRQ18	VADC0_G0SR1 and USIC0_SR3 connected to IRQ18
XMC_SCU_IRQCTRL_VADC0_G1SR0_IRQ19	VADC0_G1SR0 connected to IRQ19
XMC_SCU_IRQCTRL_USIC0_SR4_IRQ19	USIC0_SR4 connected to IRQ19
XMC_SCU_IRQCTRL_CAN0_SR2_IRQ19	CAN0_SR2 connected to IRQ19
XMC_SCU_IRQCTRL_VADC0_G1SR0_OR_USIC0_SR4_IRQ19	VADC0_G1SR0 and USIC0_SR4 connected to IRQ19
XMC_SCU_IRQCTRL_VADC0_G1SR1_IRQ20	VADC0_G1SR1 connected to IRQ20
XMC_SCU_IRQCTRL_USIC0_SR5_IRQ20	USIC0_SR5 connected to IRQ20
XMC_SCU_IRQCTRL_CAN0_SR3_IRQ20	CAN0_SR3 connected to IRQ20
XMC_SCU_IRQCTRL_CAN0_SR4_IRQ20	Deprecated: use instead XMC_SCU_IRQCTRL_CAN0_SR3_IRQ20
XMC_SCU_IRQCTRL_VADC0_G1SR1_OR_USIC0_SR5_IRQ20	VADC0_G1SR1 and USIC0_SR5 connected to IRQ20
XMC_SCU_IRQCTRL_CCU40_SR0_IRQ21	CCU40_SR0 connected to IRQ21
XMC_SCU_IRQCTRL_CCU41_SR0_IRQ21	CCU41_SR0 connected to IRQ21
XMC_SCU_IRQCTRL_USIC0_SR0_IRQ21	USIC0_SR0 connected to IRQ21
XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ21	CCU40_SR0 and CCU41_SR0 connected to IRQ21
XMC_SCU_IRQCTRL_CCU40_SR1_IRQ22	CCU40_SR1 connected to IRQ22
XMC_SCU_IRQCTRL_CCU41_SR1_IRQ22	CCU41_SR1 connected to IRQ22
XMC_SCU_IRQCTRL_USIC0_SR1_IRQ22	USIC0_SR1 connected to IRQ22
XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ22	CCU40_SR0 and CCU41_SR0 connected to IRQ22
XMC_SCU_IRQCTRL_CCU40_SR2_IRQ23	CCU40_SR2 connected to IRQ23
XMC_SCU_IRQCTRL_CCU41_SR2_IRQ23	CCU41_SR2 connected to IRQ23
XMC_SCU_IRQCTRL_USIC0_SR2_IRQ23	USIC0_SR2 connected to IRQ23
XMC_SCU_IRQCTRL_CCU40_SR2_OR_CCU41_SR2_IRQ23	CCU40_SR2 and CCU41_SR2 connected to IRQ23
XMC_SCU_IRQCTRL_CCU40_SR3_IRQ24	CCU40_SR3 connected to IRQ24
XMC_SCU_IRQCTRL_CCU41_SR3_IRQ24	CCU41_SR3 connected to IRQ24
XMC_SCU_IRQCTRL_USIC0_SR3_IRQ24	USIC0_SR3 connected to IRQ24
XMC_SCU_IRQCTRL_CCU40_SR3_OR_CCU41_SR3_IRQ24	CCU40_SR3 and CCU41_SR3 connected to IRQ24
XMC_SCU_IRQCTRL_CCU80_SR0_IRQ25	CCU80_SR0 connected to IRQ25
XMC_SCU_IRQCTRL_CCU81_SR0_IRQ25	CCU81_SR0 connected to IRQ25
XMC_SCU_IRQCTRL_USIC0_SR4_IRQ25	USIC0_SR4 connected to IRQ25
XMC_SCU_IRQCTRL_CCU80_SR0_OR_CCU81_SR0_IRQ25	CCU80_SR0 and CCU81_SR0 connected to IRQ25
XMC_SCU_IRQCTRL_CCU80_SR1_IRQ26	CCU80_SR1 connected to IRQ26
XMC_SCU_IRQCTRL_CCU81_SR1_IRQ26	CCU81_SR1 connected to IRQ26
XMC_SCU_IRQCTRL_USIC0_SR5_IRQ26	USIC0_SR5 connected to IRQ26
XMC_SCU_IRQCTRL_CCU80_SR1_OR_CCU81_SR1_IRQ26	CCU80_SR1 and CCU81_SR1 connected to IRQ26
XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ27	POSIF0_SR0 connected to IRQ27
XMC_SCU_IRQCTRL_POSIF1_SR0_IRQ27	POSIF1_SR0 connected to IRQ27
XMC_SCU_IRQCTRL_CCU40_SR3_IRQ27	CCU40_SR3 connected to IRQ27
XMC_SCU_IRQCTRL_POSIF0_SR0_OR_POSIF1_SR0_IRQ27	POSIF0_SR0 and POSIF1_SR0 connected to IRQ27
XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ28	POSIF0_SR1 connected to IRQ28
XMC_SCU_IRQCTRL_POSIF1_SR1_IRQ28	POSIF1_SR1 connected to IRQ28
XMC_SCU_IRQCTRL_ERU0_SR0_IRQ28	ERU0_SR0 connected to IRQ28
XMC_SCU_IRQCTRL_POSIF0_SR1_OR_POSIF1_SR1_IRQ28	POSIF0_SR1 and POSIF1_SR1 connected to IRQ28
XMC_SCU_IRQCTRL_LEDTS0_SR0_IRQ29	LEDTS0_SR0 connected to IRQ29
XMC_SCU_IRQCTRL_CCU40_SR1_IRQ29	CCU40_SR1 connected to IRQ29
XMC_SCU_IRQCTRL_ERU0_SR1_IRQ29	ERU0_SR1 connected to IRQ29
XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ29	LEDTS0_SR0 and CCU40_SR1 connected to IRQ29
XMC_SCU_IRQCTRL_LEDTS1_SR0_IRQ30	LEDTS1_SR0 connected to IRQ30
XMC_SCU_IRQCTRL_CCU40_SR2_IRQ30	CCU40_SR2 connected to IRQ30
XMC_SCU_IRQCTRL_ERU0_SR2_IRQ30	ERU0_SR2 connected to IRQ30
XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ30	LEDTS0_SR0 and CCU40_SR1 connected to IRQ30
XMC_SCU_IRQCTRL_BCCU0_SR0_IRQ31	BCCU0_SR0 connected to IRQ31
XMC_SCU_IRQCTRL_CCU40_SR3_IRQ31	CCU40_SR3 connected to IRQ31
XMC_SCU_IRQCTRL_ERU0_SR3_IRQ31	ERU0_SR3 connected to IRQ31
XMC_SCU_IRQCTRL_BCCU0_SR0_OR_CCU40_SR3_IRQ31	BCCU0_SR0 and CCU40_SR3 connected to IRQ31

◆ XMC_SCU_PERIPHERAL_CLOCK_t

enum XMC_SCU_PERIPHERAL_CLOCK_t

Defines the list of peripherals that support clock gating. After a master reset, only core, memories, SCU and PORT peripheral are not clock gated. The rest of the peripherals are by default clock gated. All the enum items are tabulated as per bits present in CGATSTAT0 register. Use type XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.

Note: Peripherals availability depends on device

Enumerator
XMC_SCU_PERIPHERAL_CLOCK_CCU80	CCU80 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_CCU40	CCU40 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_USIC0	USIC0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_BCCU0	BCCU0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_LEDTS0	LEDTS0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_LEDTS1	LEDTS1 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_POSIF0	POSIF0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_MATH	MATH peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_WDT	WDT peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_RTC	RTC peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_CCU81	CCU80 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_CCU41	CCU80 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_USIC1	USIC0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_LEDTS2	LEDTS1 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_POSIF1	POSIF0 peripheral clock gate.
XMC_SCU_PERIPHERAL_CLOCK_MCAN	POSIF0 peripheral clock gate.

◆ XMC_SCU_POWER_MONITOR_DELAY_t

enum XMC_SCU_POWER_MONITOR_DELAY_t

TODO

◆ XMC_SCU_POWER_MONITOR_RANGE_t

enum XMC_SCU_POWER_MONITOR_RANGE_t

TODO

◆ XMC_SCU_RESET_REASON_t

enum XMC_SCU_RESET_REASON_t

Defines the cause of last reset. The cause of last reset gets automatically stored in the SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debug purpose. All the enum items are tabulated as per bits present in SCU_RSTSTAT register. Use type XMC_SCU_RESET_REASON_t for accessing these enum parameters.

Enumerator
XMC_SCU_RESET_REASON_PORST	Reset due to Power On reset.
XMC_SCU_RESET_REASON_MASTER	Reset due to Master reset.
XMC_SCU_RESET_REASON_SW	Reset due to Software initiated reset.
XMC_SCU_RESET_REASON_LOCKUP	Reset due to CPU lockup.
XMC_SCU_RESET_REASON_FLASH	Reset due to flash error.
XMC_SCU_RESET_REASON_WATCHDOG	Reset due to watchdog.
XMC_SCU_RESET_REASON_CLOCK_LOSS	Reset due to clock loss.
XMC_SCU_RESET_REASON_PARITY_ERROR	Reset due to RAM parity error.

◆ XMC_SCU_STATUS_t

enum XMC_SCU_STATUS_t

Defines the status of SCU API execution, used to verify the SCU related API calls.

Enumerator
XMC_SCU_STATUS_OK	SCU related operation successfully completed.
XMC_SCU_STATUS_ERROR	SCU related operation failed. When API cannot fulfill request, this value is returned.
XMC_SCU_STATUS_BUSY	Cannot execute the SCU related operation request because another operation is in progress. XMC_SCU_STATUS_BUSY is returned when API is busy processing another request.

◆ XMC_SCU_SYSTEM_RESET_REQUEST_t

enum XMC_SCU_SYSTEM_RESET_REQUEST_t

Defines the reset sources that can cause device reset. These enums can be used to configure reset source in reset control RSTCON register which enables different reset sources to identify the reset cause. The SCU_RSTSTAT register can be checked by user software to determine the state of the system and for debug purpose. Use type XMC_SCU_SYSTEM_RESET_REQUEST_t for accessing these enum parameters.

Enumerator
XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR	Reset when ECC double bit error occurs.
XMC_SCU_RESET_REQUEST_CLOCK_LOSS	Reset when loss of clock occurs.
XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR	Reset when SRAM parity error occurs.
XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR	Reset when USIC0 memory parity error occurs.

Function Documentation

◆ XMC_SCU_CalcTemperature()

uint32_t XMC_SCU_CalcTemperature ( void )

Returns: uint32_t Calculate die temperature value. Range: 16 bit value.

Description: Calculates the die temperature value using ROM function.

Related APIs:: XMC_SCU_StartTempMeasurement()

◆ XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature()

void XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature ( int32_t temperature )

Parameters

temperature measured temperature using the on-chip temperature sensor

Returns: None

Description: DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy. This function start the DCO1 calibration based on temperature.

◆ XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus()

void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus ( void )

Returns: None

Description: This function clears the status of the watchdog on the DCO1 frequency

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration()

void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration ( void )

Returns: None

Description: This function stops the automatic DCO1 calibration based on the selected clock source.

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog()

void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog ( void )

Returns: None

Description: This function disables the watchdog on the DCO1 frequency

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration()

void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration	(	XMC_SCU_CLOCK_SYNC_CLKSRC_t	sync_clk,
		uint32_t	prescaler,
		uint32_t	syn_preload
	)

Parameters

sync_clk	Clock source selected as external reference. XMC_SCU_CLOCK_SYNC_CLKSRC_t
prescaler	integer( \(\frac{syn_preload \times f_{OSC}[MHz]}{48}\))
syn_preload	max. value 0x1FFF integer( \(\frac{48 \times prescaler}{f_{OSC}[MHz]}\))

Returns: None

Description: DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy. This function starts the automatic DCO1 calibration based on the selected clock source.

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog()

void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog ( void )

Returns: None

Description: This function enables the watchdog on the DCO1 frequency

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_GatePeripheralClock()

void XMC_SCU_CLOCK_GatePeripheralClock ( const XMC_SCU_PERIPHERAL_CLOCK_t peripheral )

Parameters

peripheral The peripheral for which the clock has to be gated. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral clock to be gated.

Returns: None

Description: Blocks the supply of clock to the selected peripheral.

Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks the clock supply for the selected peripheral. Software can request for individual gating of such peripheral clocks by enabling the SCU_CGATSET0 register bit field. Every bit in SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected bit fields are handled internally. Note: Clock gating shall not be activated unless the module is in reset state. So use XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral.

Related APIs:: XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock()

◆ XMC_SCU_CLOCK_GetCpuClockFrequency()

uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency ( void )

Returns: uint32_t Value of CPU clock frequency.

Description: Provides the vlaue of CPU clock frequency.

The value is stored in a global variable SystemCoreClock. It is updated when the clock configuration is done using the SCU LLD APIs. The value represents the frequency of clock used for CPU operation. Range: Value is of type uint32_t, and gives the value of frequency in Hertz.

Related APIs:: XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock()

◆ XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()

uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency ( void )

Returns: uint32_t Fast peripheral clock frequency in Hertz.

Description: Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock.

The value is derived using the bitfield PCLKSEL from CLKCR register. Peripheral clock can have 2 times the frequency of system clock if the PCLKSEL is set.

Related APIs:: XMC_SCU_CLOCK_SetFastPeripheralClockSource()

◆ XMC_SCU_CLOCK_GetPeripheralClockFrequency()

uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency ( void )

Returns: uint32_t Value of peripheral clock frequency in Hertz.

Description: Provides the vlaue of clock frequency at which the peripherals are working.

The value is derived from the CPU frequency. Range: Value is of type uint32_t. It is represented in Hertz.

Related APIs:: XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock()

◆ XMC_SCU_CLOCK_Init()

void XMC_SCU_CLOCK_Init ( const XMC_SCU_CLOCK_CONFIG_t *const config )

Parameters

config Pointer to structure holding the clock prescaler values and divider values for configuring clock generators and clock tree.
Range: Configure the members of structure XMC_SCU_CLOCK_CONFIG_t for various parameters of clock setup.

Returns: None

Description: Initializes clock generators and clock tree.

Peripheral clock and system clock are configured based on the input configuration config. The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register. The values of FDIV and IDIV can be provided as part of input configuration. The PCLK divider determines the ratio of peripheral clock to the system clock. The source of RTC clock is set based on the input configuration. SystemCoreClock variable will be updated with the value of system clock frequency. Access to protected bit fields are handled internally.

Related APIs:: XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency()

◆ XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady()

bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady ( void )

Returns: true DCO1 is synchronized to the selected XTAL frequency; false Actual DCO1 frequency is out of target

Description: This functions checks the status of the synchronisation

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_IsPeripheralClockGated()

bool XMC_SCU_CLOCK_IsPeripheralClockGated ( const XMC_SCU_PERIPHERAL_CLOCK_t peripheral )

Parameters

peripheral The peripheral for which the check for clock gating has to be done. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.

Returns: bool Status of the peripheral clock gating. Range: true if the peripheral clock is gated. false if the peripheral clock ungated(gate de-asserted).

Description: Gives the status of peripheral clock gating.

Checks the status of peripheral clock gating using the register CGATSTAT0. It is recommended to use this API before enabling the gating of any peripherals through XMC_SCU_CLOCK_GatePeripheralClock() API.

Related APIs:: XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock()

◆ XMC_SCU_CLOCK_ScaleMCLKFrequency()

void XMC_SCU_CLOCK_ScaleMCLKFrequency	(	uint32_t	idiv,
		uint32_t	fdiv
	)

Parameters

idiv	Divider value. Range: 0 to 255.
fdiv	Fractional Divider value. Range: XMC11/XMC12/XMC13 Device: 0 to 255. XMC14 Device: 0 to 1023.

Returns: None

Description: This API configures main clock (MCLK) frequency by updating user provided divider values.

The API configures main clock by setting IDIV and FDIV bit's of the CLKCR register for XMC11/XMC12/XMC13/XMC14 Device and with additional FDIV bit (FDIV[9:8]) of the CLKCR1 register settings for XMC14 device.

Related APIs:: XMC_SCU_CLOCK_SetMCLKFrequency()

◆ XMC_SCU_CLOCK_SetAdcClockSrc()

void XMC_SCU_CLOCK_SetAdcClockSrc ( XMC_SCU_CLOCK_ADCCLKSRC_t adcclk_src )

Parameters

adcclk_src Clock source selected as external reference. XMC_SCU_CLOCK_ADCCLKSRC_t

Returns: None

Description: ADC converter clock (fCONV) selection

Note: Only available for XMC1400 series

◆ XMC_SCU_CLOCK_SetFastPeripheralClockSource()

void XMC_SCU_CLOCK_SetFastPeripheralClockSource ( const XMC_SCU_CLOCK_PCLKSRC_t source )

Parameters

source Fast peripheral clock source.
Range: Use type XMC_SCU_CLOCK_PCLKSRC_t to identify the clock source.
XMC_SCU_CLOCK_PCLKSRC_MCLK- Use MCLK as the peripheral clock.
XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK- peripheral clock will be 2 times the MCLK frequency.

Returns: None

Description: Configures the source of peripheral clock.

The peripheral clock can be either same as MCLK or twice the frequency of MCLK.

Related APIs:: XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()

◆ XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode()

void XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode ( XMC_SCU_CLOCK_OSCHP_MODE_t mode )

Parameters

mode	Oscillator mode. XMC_SCU_CLOCK_OSCHP_MODE_t

Returns: None

Description: Configure functional mode of the OSCHP.

◆ XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode()

void XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode ( XMC_SCU_CLOCK_OSCLP_MODE_t mode )

Parameters

mode	Oscillator mode. XMC_SCU_CLOCK_OSCLP_MODE_t

Returns: None

Description: Configure functional mode of the OSCLP.

◆ XMC_SCU_CLOCK_SetMCLKFrequency()

void XMC_SCU_CLOCK_SetMCLKFrequency ( uint32_t freq_khz )

Parameters

freq_khz Required MCLK frequency value in kHz.
Range: XMC11/XMC12/XMC13 Device: 125 to 32000. XMC14 Device: 188 to 48000 when DCO1 is clock source for clock control unit. 79 to 48000 when OSC_HP is clock source for clock control unit.

Returns: None

Description: This API configures main clock (MCLK) frequency to requested frequency value.

The API configures main clock by setting IDIV and FDIV bit's of the CLKCR register for XMC11/XMC12/XMC13/XMC14 Device and with additional FDIV bit (FDIV[9:8]) of the CLKCR1 register settings for XMC14 device.

Related APIs:: XMC_SCU_CLOCK_ScaleMCLKFrequency()

◆ XMC_SCU_CLOCK_UngatePeripheralClock()

void XMC_SCU_CLOCK_UngatePeripheralClock ( const XMC_SCU_PERIPHERAL_CLOCK_t peripheral )

Parameters

peripheral The peripheral for which the clock has to be ungated. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.

Returns: None

Description: Enables the supply of clock to the selected peripheral.

By default when the device powers on, the peripheral clock will be gated for the peripherals that support clock gating. The peripheral clock should be enabled before using it for any functionality. fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Software can request for individual ungating of such peripheral clocks by setting respective bits in the SCU_CGATCLR0 register.

Related APIs:: XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock()

◆ XMC_SCU_DisablePrefetchUnit()

void XMC_SCU_DisablePrefetchUnit ( void )

This function disables the Prefetch Unit (PFU). The purpose of the Prefetch unit is to reduce the Flash latency gap at higher system frequencies to increase the instruction per cycle performance.

Note: Only available for XMC1400 series

◆ XMC_SCU_EnablePrefetchUnit()

void XMC_SCU_EnablePrefetchUnit ( void )

This function enables the Prefetch Unit (PFU). The purpose of the Prefetch unit is to reduce the Flash latency gap at higher system frequencies to increase the instruction per cycle performance.

Note: Only available for XMC1400 series

◆ XMC_SCU_GetBMI()

uint32_t XMC_SCU_GetBMI ( void )

Returns: uint32_t Current BMI value.

Description: This procedure initiates installation of a new BMI value. In particular, it can be used as well as to restore the state upon delivery for a device already in User Productive mode.

// Switch to ASC Bootstrap Loader
bmi_value = XMC_SCU_GetBMI();
if ((bmi_value & 0x000000ffU) != XMC_SCU_BMI_HWCFG_ASC)
{
  XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC, 0);
}

< Boot Mode Index (BMI) address holding information about start-up mode and debug configuration of the device.

◆ XMC_SCU_GetMirrorStatus()

uint32_t XMC_SCU_GetMirrorStatus ( void )

Returns: uint32_t Status of the register mirror update.
Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined using OR operation.

Description: Provides the status of hibernate domain register update, when the respective mirror registers are changed.

The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register representing the communication of changed value of a mirror register to its corresponding register in the hibernate domain. The bit fields of the register indicate that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface is busy with executing the previous operation.
Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose.

◆ XMC_SCU_GetTemperature()

uint32_t XMC_SCU_GetTemperature ( void )

Returns: uint32_t Raw die temperature value. Range: 16 bit value.

Description: Provides the raw die temperature value.

The API reads temperature measurement result from SCU_ANALOG->ANATSEMON bit fields.

Related APIs:: XMC_SCU_StartTempMeasurement()

◆ XMC_SCU_HighTemperature()

bool XMC_SCU_HighTemperature ( void )

Returns: bool Result of checking whether the die temperature is more than the upper threshold.
Range: false if temperature is below the upper threshold. true if temperature has exceeded the upper threshold configured in ANATSEIH register.

Description: Check if the temperature has exceeded the upper threshold value.

The API checks for TSE_HIGH bit (TSE Compare High Temperature Event Status bit) of SRRAW register. The bit will be set when the TSE_MON value in ANATSEMON register exceeds the value of TSE_IH value in ANATSEIH register.

Related APIs:: XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_LowTemperature()

◆ XMC_SCU_INTERRUPT_ClearEventStatus()

void XMC_SCU_INTERRUPT_ClearEventStatus ( const XMC_SCU_INTERRUPT_EVENT_t event )

Parameters

event Bit mask of the events to clear. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns: None

Description: Clears the event status bit in SRRAW register.

The events are cleared by writing value 1 to their bit positions in the SRCLR register. The API can be used when polling method is used. After detecting the event, the event status should be cleared using software to detect the event again.

Related APIs:: XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent()

◆ XMC_SCU_INTERRUPT_DisableEvent()

void XMC_SCU_INTERRUPT_DisableEvent ( const XMC_SCU_INTERRUPT_EVENT_t event )

Parameters

event Bit mask of the event to disable. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns: None

Description: Disables generation of interrupt on occurrence of the input event.

The events are disabled by resetting the respective bit fields in the SRMSK register.

Related APIs:: NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()

◆ XMC_SCU_INTERRUPT_EnableEvent()

void XMC_SCU_INTERRUPT_EnableEvent ( const XMC_SCU_INTERRUPT_EVENT_t event )

Parameters

event Bit mask of the event to enable. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns: None

Description: Enables the generation of interrupt for the input events.

The events are enabled by setting the respective bit fields in the SRMSK register.
Note: User should separately enable the NVIC node responsible for handling the SCU interrupt. The interrupt will be generated when the respective event occurs.

Related APIs:: NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()

◆ XMC_SCU_INTERRUPT_SetEventHandler()

XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler	(	const XMC_SCU_INTERRUPT_EVENT_t	event,
		const XMC_SCU_INTERRUPT_EVENT_HANDLER_t	handler
	)

Parameters

event	The event for which the interrupt handler is to be configured. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
handler	Name of the function to be executed when the event if detected. Range: The function accepts no arguments and returns no value.

Returns: XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.
Range: XMC_SCU_STATUS_OK if the event handler is successfully configured.
XMC_SCU_STATUS_ERROR if the input event is invalid.

Description: Assigns the event handler function to be executed on occurrence of the selected event.

If the input event is valid, the handler function will be assigned to a table to be executed when the interrupt is generated and the event status is set in the event status register. By using this API, polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed. It checks for status flags of events which can generate the interrupt. The handler function will be executed if the event flag is set.

Related APIs:: XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus()

◆ XMC_SCU_INTERRUPT_TriggerEvent()

void XMC_SCU_INTERRUPT_TriggerEvent ( const XMC_SCU_INTERRUPT_EVENT_t event )

Parameters

event Bit mask of the event to be triggered. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns: None

Description: Triggers the event as if the hardware raised it.

Event will be triggered by setting the respective bitfield in the SRSET register.
Note: User should enable the NVIC node that handles the respective event for interrupt generation.

Related APIs:: NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus()

◆ XMC_SCU_INTERUPT_GetEventStatus()

XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus ( void )

Returns: uint32_t Status of the SCU events.

Description: Provides the status of all SCU events.

The status is read from the SRRAW register. To check the status of a particular event, the returned value should be masked with the bit mask of the event. The bitmask of events can be obtained using the type XMC_SCU_INTERRUPT_EVENT_t. Multiple events' status can be checked by combining the bit masks using OR operation. After detecting the event, the event status should be cleared using software to detect the event again.

Related APIs:: XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler()

◆ XMC_SCU_IRQHandler()

void XMC_SCU_IRQHandler ( uint32_t sr_num )

Parameters

sr_num Service request number identifying the SCU interrupt generated.
Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.
But XMC1x devices support 3 interrupt nodes.

Returns: None

Description: A common function to execute callback functions for multiple events.

It checks for the status of events which can generate the interrupt with the selected service request. If the event is set, the corresponding callback function will be executed. It also clears the event status bit.
Note: This is an internal function. It should not be called by the user application.

Related APIs:: XMC_SCU_INTERRUPT_SetEventHandler()

◆ XMC_SCU_IsTempMeasurementDone()

bool XMC_SCU_IsTempMeasurementDone ( void )

Returns: true DTS Measurement Done; false DTS Measurement not Done

Description: This functions checks the status of the DTS Measurement completion.

Related APIs:: XMC_SCU_StartTempMeasurement()

◆ XMC_SCU_LockProtectedBits()

void XMC_SCU_LockProtectedBits ( void )

Returns: None

Description

Locks access to protected bit fields of the SCU.

The bit protection scheme prevents changing selected register bits by unauthorized code. Bit protection scheme is enabled by writing 000000C3H to PASSWD register. By writing this value, the API is setting the MODE bit field to bit protection enabled state.
List of Protected Register Bit Fields are mentioned below.

Register	Bit fields
SCU_CLKCR	FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0	All bits
SCU_CGATCLR0	All bits
SCU_ANAOFFSET	ADJL_OFFSET
VADC0_ACCPROT0	All bits
VADC0_ACCPROT1	All bits

Related APIs:: XMC_SCU_UnlockProtectedBits()

◆ XMC_SCU_LowTemperature()

bool XMC_SCU_LowTemperature ( void )

Returns: bool Result of checking whether the die temperature is less than the lower threshold.
Range: false if temperature is higher than the lower threshold. true if temperature has dropped below the lower threshold configured in ANATSEIL register.

Description: Check if the temperature has dropped below the lower threshold value.

The API checks for TSE_LOW bit (TSE Compare Low Temperature Event Status bit) of SRRAW register. The bit will be set when the TSE_MON value in ANATSEMON register drops below the value of TSE_IL value in ANATSEIL register.

Related APIs:: XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_HighTemperature()

◆ XMC_SCU_POWER_DisableMonitor()

void XMC_SCU_POWER_DisableMonitor ( void )

Returns: None

Description: Disables VDEL detector

◆ XMC_SCU_POWER_EnableMonitor()

void XMC_SCU_POWER_EnableMonitor	(	XMC_SCU_POWER_MONITOR_RANGE_t	range,
		XMC_SCU_POWER_MONITOR_DELAY_t	delay
	)

Parameters

range	VDEL Range Select XMC_SCU_POWER_MONITOR_RANGE_t
delay	VDEL Timing Setting XMC_SCU_POWER_MONITOR_DELAY_t

Returns: None

Description: Enables VDEL detector. VDEL detector compares the supply voltage against a pre-warning threshold voltage

Note: Brown Out Trap need to be enabled previously

◆ XMC_SCU_RESET_AssertMasterReset()

void XMC_SCU_RESET_AssertMasterReset ( void )

Returns: None

Description: Trigger device master reset.

The API triggers master reset by setting the MRSTEN bit of RSTCON register. It also internally triggers system reset. Almost all the logics of the device are affected by this reset.

Related APIs:: XMC_SCU_RESET_EnableResetRequest()

◆ XMC_SCU_RESET_ClearDeviceResetReason()

void XMC_SCU_RESET_ClearDeviceResetReason ( void )

Returns: None

Description: Clears the reset reason bits in the reset status register.

Clearing of the reset status information in the SCU_RSTSTAT register via register bit RSTCLR.RSCLR is strongly recommended to ensure a clear indication of the cause of next reset.

Related APIs:: XMC_SCU_RESET_GetDeviceResetReason()

◆ XMC_SCU_RESET_EnableResetRequest()

void XMC_SCU_RESET_EnableResetRequest ( uint32_t request )

Parameters

request Reset source to trigger the device reset.
Range: Use type XMC_SCU_SYSTEM_RESET_REQUEST_t to identify the reset source.
XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR- Reset when flash memory double bit error is detected.
XMC_SCU_RESET_REQUEST_CLOCK_LOSS- Reset when loss of clock is detected.
XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR- Reset when SRAM parity error is detected.
XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR- Reset when USIC0 SRAM parity error is detected.

Returns: None

Description: Configures trigger for system reset from the selected source.

The API configures the reset source specific bit in the RSTCON register. Multiple reset sources can be combined using OR operation. By enabling the reset using this API will not trigger the reset. The reset will happen when the configured source event is detected.

Related APIs:: XMC_SCU_RESET_AssertMasterReset()

◆ XMC_SCU_RESET_GetDeviceResetReason()

uint32_t XMC_SCU_RESET_GetDeviceResetReason ( void )

Returns: uint32_t Status representing the reason for device reset.

Description: Provides the value representing the reason for device reset.

The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the returned word is representative of a last reset cause. The returned value should be appropriately masked to check the cause of reset. The cause of the last reset gets automatically stored in the SCU_RSTSTAT register. The reset status shall be reset after each startup in order to ensure consistent source indication after the next reset. Range: The type XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause.

Related APIs:: XMC_SCU_RESET_ClearDeviceResetReason()

◆ XMC_SCU_SetBMI()

uint32_t XMC_SCU_SetBMI	(	uint32_t	flags,
		uint8_t	timeout
	)

Parameters

flags

may be any of:
XMC_SCU_BMI_HWCFG_CAN_BSL (only available for XMC1400 series with CAN Module)
XMC_SCU_BMI_HWCFG_CAN_BSLTO (only available for XMC1400 series with CAN Module)
XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (only available for XMC1400 series with CAN Module)
XMC_SCU_BMI_HWCFG_ASC_BSL
XMC_SCU_BMI_HWCFG_UPM
XMC_SCU_BMI_HWCFG_UMD
XMC_SCU_BMI_HWCFG_UMHAR
XMC_SCU_BMI_HWCFG_SSC_BSL
XMC_SCU_BMI_HWCFG_ASC_BSLTO
XMC_SCU_BMI_HWCFG_SSC_BSLTO
XMC_SCU_BMI_HWCFG_SBSL

optionally OR'd together with any of (only available for XMC1400 series):
XMC_SCU_BMI_HWCFG_PINDIS optionally OR'd together with any of:
XMC_SCU_BMI_DAPTYP_SWD
XMC_SCU_BMI_DAPTYP_SPD

optionally OR'd together with any of:
XMC_SCU_BMI_DAPDIS_CHANNEL_0
XMC_SCU_BMI_DAPDIS_CHANNEL_1

optionally OR'd together with any of (only available for XMC1400 series with CAN Module):
XMC_SCU_BMI_CANCLK_DCO1
XMC_SCU_BMI_CANCLK_OSCHP

timeout Only relevant if a start up mode is selected that uses timeout. The time-out duration is BSLTO*2664000 MCLK cycles, the supported time-out range is 0.3-5s (333...4995ms)

Returns: false only upon error, if OK the procedure triggers a reset and does not return to calling routine

Description: This procedure initiates installation of a new BMI value. In particular, it can be used as well as to restore the state upon delivery for a device already in User Productive mode.

// Switch to ASC Bootstrap Loader
XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC_BSL, 0);
// Switch to Debug user mode SWD1 (pins P1.3 and P1.2)
XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_UMD | XMC_SCU_BMI_DAPTYP_SWD | XMC_SCU_BMI_DAPDIS_CHANNEL_1, 0);

◆ XMC_SCU_SetCcuTriggerHigh()

void XMC_SCU_SetCcuTriggerHigh ( const uint32_t trigger )

Parameters

trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits in the register CCUCON.
Range: Use type XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be combined using OR operation.

Returns: None

Description: Generates active edge(low to high) trigger for multiple CCU units at the same time.

Before executing this API, all the required CCU timers should configure external start. The edge of the start signal should be selected as active edge. The input signal for the CCU slice should be selected as SCU input. The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering the timer using this API.

Related APIs:: XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()

◆ XMC_SCU_SetCcuTriggerLow()

void XMC_SCU_SetCcuTriggerLow ( const uint32_t trigger )

Parameters

trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits in the register CCUCON.
Range: Use type XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be combined using OR operation.

Returns: None

Description: Generates passive edge(high to low) trigger for multiple CCU units at the same time.

Before executing this API, all the required CCU timers should configure external start. The edge of the start signal should be selected as passive edge. The input signal for the CCU slice should be selected as SCU input. The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering the timer using this API.

Related APIs:: XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()

◆ XMC_SCU_SetInterruptControl()

void XMC_SCU_SetInterruptControl	(	uint8_t	irq_number,
		XMC_SCU_IRQCTRL_t	source
	)

This function selects service request source for a NVIC interrupt node. The XMC1400 series has up to 54 peripheral service requests. The Cortex M0 however has 32 interrupts available for peripherals. This function allows you to select which 32 peripheral requests of the 54 the CPU should react on.

Parameters

irq_number	Interrupt number, 0 to 31
source	Peripheral service request. See XMC_SCU_IRQCTRL_t

Note: Only available for XMC1400 series

◆ XMC_SCU_SetRawTempLimits()

void XMC_SCU_SetRawTempLimits	(	const uint32_t	lower_temp,
		const uint32_t	upper_temp
	)

Parameters

lower_temp	Lower threshold value for the die temperature. Range: 0 to 65535(16 bit unsigned value).
upper_temp	Upper threshold value for the die temperature. Range: 0 to 65535(16 bit unsigned value).

Returns: None

Description

Configures upper and lower thresholds of die temperature as raw digital values into temperature sensor.

The API configures ANATSEIH and ANATSEIL registers for upper and lower die temperature threshold limits respectively.
It is recommended to use following steps:

Call XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.
Call XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.
Finally call XMC_SCU_StartTempMeasurement to start temperature measurement.

Related APIs:: XMC_SCU_StopTempMeasurement(), XMC_SCU_StartTempMeasurement()

◆ XMC_SCU_SetTempHighLimit()

XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit ( uint32_t limit )

Parameters

limit Kelvin degree temperature higher compare limit in range [233,388]

Returns: XMC_SCU_STATUS_t status of limit installation

Description: Set higher temperature compare limit. A high temperature interrupt (SCU_IRQ1) is triggered if Tchip > limit and the event and interrupt are enabled. Alternatively XMC_SCU_HighTemperature() can be used to check the status.

Related APIs:: XMC_SCU_HighTemperature()

◆ XMC_SCU_SetTempLowLimit()

XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit ( uint32_t limit )

Parameters

limit Kelvin degree temperature lower compare limit in range [233,388]

Returns: XMC_SCU_STATUS_t status of limit installation

Description: Set lower temperature compare limit. A low temperature interrupt (SCU_IRQ1) is triggered if Tchip < limit and the event and interrupt are enabled. Alternatively XMC_SCU_LowTemperature() can be used to check the status.

Related APIs:: XMC_SCU_LowTemperature()

◆ XMC_SCU_StartTempMeasurement()

void XMC_SCU_StartTempMeasurement ( void )

Returns: XMC_SCU_STATUS_t Status of starting the temperature measurement.
Range: Use type XMC_SCU_STATUS_t to identify the result.
XMC_SCU_STATUS_OK- Temperature measurement started successfully.
Always returns the above status.

Description

Starts die temperature measurement using internal temperature sensor.

The API, enables die temperature measurement and waits for about 10000 cycles until temperature measurement result is available on SCU_ANALOG->ANATSEMON bit fields.
It is recommended to use following steps:

Call XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.
Call XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.
Call XMC_SCU_StartTempMeasurement to start temperature measurement.
Read die temperature value using XMC_SCU_GetTemperature API.

Related APIs:: XMC_SCU_StopTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature()

◆ XMC_SCU_StopTempMeasurement()

void XMC_SCU_StopTempMeasurement ( void )

Returns: None

Description: Stops the die temperature measurement.

Die temperature measurement is stopped by disabling the sensor using TSE_EN bit of ANATSECTRL register.

Related APIs:: XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature()

◆ XMC_SCU_SupplyMonitorInit()

void XMC_SCU_SupplyMonitorInit ( const XMC_SCU_SUPPLYMONITOR_t * obj )

Parameters

obj	Pointer to data structure consisting voltage monitoring block configuration. Range: Use type XMC_SCU_SUPPLYMONITOR_t for detailed description of structure members.

Returns: None

Description: Initializes power supply monitoring unit.

Supply voltage monitoring block consist of 2 detectors namely External voltage detector (VDEL) and External brownout detector (BDE) in the EVR that are used to monitor the VDDP. VDEL detector compares the supply voltage against a pre-warning threshold voltage ext_supply_threshold. The threshold level is programmable via register ANAVDEL.VDEL_SELECT. An interrupt if enabled via enable_prewarning_int, will be triggered if a level below this threshold is detected and the flag, VDDPI, in SRRAW register bit is set. Similarly interrupts can be enabled for the events of VCLIP and prewarning, using the structure members, enable_vclip_int and enable_prewarning_int. The handlers for these interrupts have to be explicitly defined using the API XMC_SCU_INTERRUPT_SetEventHandler().

Related APIs:: XMC_SCU_INTERRUPT_SetEventHandler()

◆ XMC_SCU_UnlockProtectedBits()

void XMC_SCU_UnlockProtectedBits ( void )

Returns: None

Description

Unlocks access to protected bit fields of the SCU.

The bit protection scheme prevents changing selected register bits by unauthorized code. Bit protection scheme can be temporarily(for 32 MCLK cycles) disabled by writing 000000C0H to PASSWD register. By writing this value, the API is setting the MODE bit field to bit protection disabled state. The API waits for the protection to be disabled after changing the MODE.
User can change the values of the protected bit fields within 32 MCLK cycles. After 32 MCLK cycles the lock will be enabled automatically. List of Protected Register Bit Fields are mentioned below.

Register	Bit fields
SCU_CLKCR	FDIV, IDIV, PCLKSEL, RTCLKSEL
SCU_CGATSET0	All bits
SCU_CGATCLR0	All bits
SCU_ANAOFFSET	ADJL_OFFSET
VADC0_ACCPROT0	All bits
VADC0_ACCPROT1	All bits

Related APIs:: XMC_SCU_LockProtectedBits()

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ XMC_BMI_ADDR

◆ XMC_SCU_BMI_CANCLK_DCO1

◆ XMC_SCU_BMI_CANCLK_OSCHP

◆ XMC_SCU_BMI_DAPDIS_CHANNEL_0

◆ XMC_SCU_BMI_DAPDIS_CHANNEL_1

◆ XMC_SCU_BMI_DAPTYP_SPD

◆ XMC_SCU_BMI_DAPTYP_SWD

◆ XMC_SCU_BMI_HWCFG_ASC_BSL

◆ XMC_SCU_BMI_HWCFG_ASC_BSLTO

◆ XMC_SCU_BMI_HWCFG_CAN_BSL

◆ XMC_SCU_BMI_HWCFG_CAN_BSLTO

◆ XMC_SCU_BMI_HWCFG_PINDIS

◆ XMC_SCU_BMI_HWCFG_SBSL

◆ XMC_SCU_BMI_HWCFG_SBSL_CANOPEN

◆ XMC_SCU_BMI_HWCFG_SSC_BSL

◆ XMC_SCU_BMI_HWCFG_SSC_BSLTO

◆ XMC_SCU_BMI_HWCFG_UMD

◆ XMC_SCU_BMI_HWCFG_UMHAR

◆ XMC_SCU_BMI_HWCFG_UPM

◆ XMC_SCU_INTERRUPT_EVENT_ACMP0

◆ XMC_SCU_INTERRUPT_EVENT_ACMP1

◆ XMC_SCU_INTERRUPT_EVENT_ACMP2

◆ XMC_SCU_INTERRUPT_EVENT_ACMP3

◆ XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC

◆ XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED

◆ XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR

◆ XMC_SCU_INTERRUPT_EVENT_LOCI

◆ XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK

◆ XMC_SCU_INTERRUPT_EVENT_ORC0

◆ XMC_SCU_INTERRUPT_EVENT_ORC1

◆ XMC_SCU_INTERRUPT_EVENT_ORC2

◆ XMC_SCU_INTERRUPT_EVENT_ORC3

◆ XMC_SCU_INTERRUPT_EVENT_ORC4

◆ XMC_SCU_INTERRUPT_EVENT_ORC5

◆ XMC_SCU_INTERRUPT_EVENT_ORC6

◆ XMC_SCU_INTERRUPT_EVENT_ORC7

◆ XMC_SCU_INTERRUPT_EVENT_PEMCAN

◆ XMC_SCU_INTERRUPT_EVENT_PESRAM

◆ XMC_SCU_INTERRUPT_EVENT_PEUSIC0

◆ XMC_SCU_INTERRUPT_EVENT_PEUSIC1

◆ XMC_SCU_INTERRUPT_EVENT_RTC_ALARM

◆ XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC

◆ XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED

◆ XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED

◆ XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED

◆ XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED

◆ XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED

◆ XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL

◆ XMC_SCU_INTERRUPT_EVENT_TSE_DONE

◆ XMC_SCU_INTERRUPT_EVENT_TSE_HIGH

◆ XMC_SCU_INTERRUPT_EVENT_TSE_LOW

◆ XMC_SCU_INTERRUPT_EVENT_VCLIP

◆ XMC_SCU_INTERRUPT_EVENT_VDDPI

◆ XMC_SCU_INTERRUPT_EVENT_VDROP

◆ XMC_SCU_INTERRUPT_EVENT_WDT_WARN

Typedef Documentation

◆ XMC_SCU_INTERRUPT_EVENT_HANDLER_t

◆ XMC_SCU_INTERRUPT_EVENT_t

Enumeration Type Documentation

◆ XMC_SCU_CCU_TRIGGER_t

◆ XMC_SCU_CLOCK_ADCCLKSRC_t

◆ XMC_SCU_CLOCK_DCLKSRC_t

◆ XMC_SCU_CLOCK_OSCHP_MODE_t

◆ XMC_SCU_CLOCK_OSCLP_MODE_t

◆ XMC_SCU_CLOCK_PCLKSRC_t

◆ XMC_SCU_CLOCK_RTCCLKSRC_t

◆ XMC_SCU_CLOCK_SYNC_CLKSRC_t

◆ XMC_SCU_IRQCTRL_t

◆ XMC_SCU_PERIPHERAL_CLOCK_t

◆ XMC_SCU_POWER_MONITOR_DELAY_t

◆ XMC_SCU_POWER_MONITOR_RANGE_t

◆ XMC_SCU_RESET_REASON_t

◆ XMC_SCU_STATUS_t