cy_stc_smif_config_t Struct Reference

Description

The SMIF configuration structure.

Data Fields
uint32_t	mode
	Specifies the mode of operation cy_en_smif_mode_t. More...
uint32_t	deselectDelay
	Specifies the minimum duration of SPI de-selection between SPI transfers: More...
uint32_t	setupDelay
	Specifies the duration between "spi_select_out[]" becomes low/'0') to 1st "spi_clk_out" edge: "0": 0 memory interface clock cycles + min. More...
uint32_t	holdDelay
	Specifies the duration between last "spi_clk_out" edge to "spi_select_out[]" becomes high/'1'): "0": 0 memory interface clock cycles + min. More...
uint32_t	rxClockSel
	Specifies the clock source for the receiver clock cy_en_smif_clk_select_t. More...
uint32_t	blockEvent
	Specifies what happens when there is a Read from an empty RX FIFO or a Write to a full TX FIFO. More...

Field Documentation

uint32_t cy_stc_smif_config_t::mode

Specifies the mode of operation cy_en_smif_mode_t.

uint32_t cy_stc_smif_config_t::deselectDelay

Specifies the minimum duration of SPI de-selection between SPI transfers:

• "0": 1 clock cycle.
• "1": 2 clock cycles.
• "2": 3 clock cycles.
• "3": 4 clock cycles.
• "4": 5 clock cycles.
• "5": 6 clock cycles.
• "6": 7 clock cycles.
• "7": 8 clock cycles.

uint32_t cy_stc_smif_config_t::setupDelay

Specifies the duration between "spi_select_out[]" becomes low/'0') to 1st "spi_clk_out" edge: "0": 0 memory interface clock cycles + min.

duration (see below). "1": 1 memory interface clock cycle + min. duration (see below). "2": 2 memory interface clock cycles + min. duration (see below). "3": 3 memory interface clock cycles + min. duration (see below). In addition to the number of cycles selected here there is a min. duration of:

• 1 memory interface clock cycle (= 2 clk_if cycle) for SDR timing (CLOCK_IF_TX_SEL = 0)
• 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1)

uint32_t cy_stc_smif_config_t::holdDelay

Specifies the duration between last "spi_clk_out" edge to "spi_select_out[]" becomes high/'1'): "0": 0 memory interface clock cycles + min.

duration (see below). "1": 1 memory interface clock cycle + min. duration (see below). "2": 2 memory interface clock cycles + min. duration (see below). "3": 3 memory interface clock cycles + min. duration (see below). In addition to the number of cycles selected here there is a min. duration of:

• 1/2 memory interface clock cycle (= 1 clk_if cycles) for SDR timing (CLOCK_IF_TX_SEL = 0)
• 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1)

uint32_t cy_stc_smif_config_t::rxClockSel

Specifies the clock source for the receiver clock cy_en_smif_clk_select_t.

uint32_t cy_stc_smif_config_t::blockEvent

Specifies what happens when there is a Read from an empty RX FIFO or a Write to a full TX FIFO.

cy_en_smif_error_event_t.