General Description

Data Structures
union	BTSS_DMAC_CONTROL_REG_t
	DMAC Control register configuration. More...

union	BTSS_DMAC_CONFIG_REG_t
	DMAC Config register configuration. More...

struct	BTSS_DMAC_LLI_DESC_t
	DMAC Next Linked List Descriptor. More...

struct	BTSS_DMAC_MSG_t
	DMAC messaging for internal queue. More...

struct	BTSS_DMAC_APP_REQUEST_t
	DMA transfer request control block, to be used with a call to dma_RequestTransfer. More...

Enumerations
enum	BTSS_DMAC_CONTROL_REG_DATAWIDTH_t { BTSS_DMAC_CONTROL_REG_DATAWIDTH_1BYTE = 0, BTSS_DMAC_CONTROL_REG_DATAWIDTH_HALF_WORD = 1, BTSS_DMAC_CONTROL_REG_DATAWIDTH_WORD = 2 }
	DMAC Control register - Transfer data width configuration.

enum	BTSS_DMAC_CONTROL_REG_BURST_SIZE_t { BTSS_DMAC_CONTROL_REG_BURST_SIZE_1 = 0, BTSS_DMAC_CONTROL_REG_BURST_SIZE_4 = 1, BTSS_DMAC_CONTROL_REG_BURST_SIZE_8 = 2, BTSS_DMAC_CONTROL_REG_BURST_SIZE_16 = 3, BTSS_DMAC_CONTROL_REG_BURST_SIZE_32 = 4, BTSS_DMAC_CONTROL_REG_BURST_SIZE_64 = 5, BTSS_DMAC_CONTROL_REG_BURST_SIZE_128 = 6, BTSS_DMAC_CONTROL_REG_BURST_SIZE_256 = 7 }
	DMAC Control register - Transfer burst size configuration.

enum	BTSS_DMAC_CONTROL_LINE_t { BTSS_DMAC_CONTROL_LINE_NONE = 0, BTSS_DMAC_CONTROL_LINE_SRC_HCI_UART = 0, BTSS_DMAC_CONTROL_LINE_DST_HCI_UART = 0, BTSS_DMAC_CONTROL_LINE_DST_MXTDM0 = 4, BTSS_DMAC_CONTROL_LINE_SRC_MXTDM0 = 5, BTSS_DMAC_CONTROL_LINE_DST_MXTDM1 = 6, BTSS_DMAC_CONTROL_LINE_SRC_MXTDM1 = 7, BTSS_DMAC_CONTROL_LINE_SRC_SCB1 = 9, BTSS_DMAC_CONTROL_LINE_SRC_SCB0 = 10, BTSS_DMAC_CONTROL_LINE_DST_SCB0 = 11, BTSS_DMAC_CONTROL_LINE_DST_SCB1 = 13, BTSS_DMAC_CONTROL_LINE_SRC_SCB2 = 14, BTSS_DMAC_CONTROL_LINE_DST_SCB2 = 15 }
	DMAC Control register - DMAC Flow Control Lines configuration. More...

enum	BTSS_DMAC_CONFIG_REG_FLOWCONTROL_t { BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_MEMORY = 0, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_PERIPH_NO_FLOW = 1, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_MEMORY_NO_FLOW = 2, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_NO_FLOW = 3, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_DEST_FLOW = 4, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_PERIPH_DEST_FLOW = 5, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_MEMORY_SRC_FLOW = 6, BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_SRC_FLOW = 7 }
	DMAC Config register - Flow control type configuration. More...

enum	BTSS_DMAC_REQ_STATUS_t { BTSS_DMA_REQ_STATUS_NO_PENDING = 0, BTSS_DMA_REQ_STATUS_IN_PROGRESS = 1, BTSS_DMA_REQ_STATUS_WAITING_IN_QUEUE = 2, BTSS_DMA_REQ_STATUS_NOT_IN_QUEUE = 3 }

Enumeration Type Documentation

enum BTSS_DMAC_CONTROL_LINE_t

DMAC Control register - DMAC Flow Control Lines configuration.

Enumerator
BTSS_DMAC_CONTROL_LINE_NONE	None.
BTSS_DMAC_CONTROL_LINE_DST_MXTDM0	mxtdm0 Tx DMA flow control line
BTSS_DMAC_CONTROL_LINE_SRC_MXTDM0	mxtdm0 Rx DMA flow control line
BTSS_DMAC_CONTROL_LINE_DST_MXTDM1	mxtdm1 Tx DMA flow control line
BTSS_DMAC_CONTROL_LINE_SRC_MXTDM1	mxtdm1 Rx DMA flow control line
BTSS_DMAC_CONTROL_LINE_SRC_SCB1	scb1 Rx DMA flow control line
BTSS_DMAC_CONTROL_LINE_SRC_SCB0	scb0 Rx DMA flow control line
BTSS_DMAC_CONTROL_LINE_DST_SCB0	scb0 Tx DMA flow control line
BTSS_DMAC_CONTROL_LINE_DST_SCB1	scb Tx DMA flow control line
BTSS_DMAC_CONTROL_LINE_SRC_SCB2	scb2 Rx DMA flow control line
BTSS_DMAC_CONTROL_LINE_DST_SCB2	scb2 Tx DMA flow control line

enum BTSS_DMAC_CONFIG_REG_FLOWCONTROL_t

DMAC Config register - Flow control type configuration.

Enumerator
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_MEMORY	memory-to-memory transfer.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_PERIPH_NO_FLOW	memory-to-peripheral transfer without flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_MEMORY_NO_FLOW	peripheral-to-memory transfer without flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_NO_FLOW	peripheral-to-peripheral transfer without flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_DEST_FLOW	peripheral-to-peripheral transfer with the destination peripheral providing flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_MEMORY_TO_PERIPH_DEST_FLOW	memory-to-peripheral transfer with the destination peripheral providing flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_MEMORY_SRC_FLOW	peripheral-to-memory transfer with the source peripheral providing flow control.
BTSS_DMAC_CONFIG_REG_FLOWCNTRL_PERIPH_TO_PERIPH_SRC_FLOW	peripheral-to-peripheral transfer with the source peripheral providing flow control.

General Description

Data Structures

Enumerations

Enumeration Type Documentation