Data Structures

General Description

Data Structures
struct	cy_stc_adccomp_lpcomp_dc_config_t
struct	cy_stc_adccomp_lpcomp_ntd_config_t
struct	cy_stc_adccomp_lpcomp_config_t
struct	cy_stc_adccomp_adc_context_t
	The ADC driver context structure - it stores the offset values for DC voltage measurement. More...
struct	cy_stc_adccomp_adc_dc_config_t
struct	cy_stc_adccomp_adc_mic_config_t
struct	cy_stc_adccomp_adc_config_t

Typedefs
typedef void(*	CY_ADCCOMP_IRQ_THREAD_CB_t )(void)
	ADCCOMP - Interrupt Callback from IRQ Thread.

Enumerations
enum	cy_en_adccomp_lpcomp_id_t {   CY_ADCCOMP_LPCOMP_1 = 1,   CY_ADCCOMP_LPCOMP_2 = 2 }
	< ADCCOMP register configuration More...
enum	cy_en_adccomp_lpcomp_mode_t {   CY_ADCCOMP_LPCOMP_DC,   CY_ADCCOMP_LPCOMP_NTD }
enum	cy_en_adccomp_adc_dc_channel_t {   CY_ADCCOMP_ADC_IN_GPIO0,   CY_ADCCOMP_ADC_IN_GPIO1,   CY_ADCCOMP_ADC_IN_GPIO2,   CY_ADCCOMP_ADC_IN_GPIO3,   CY_ADCCOMP_ADC_IN_GPIO4,   CY_ADCCOMP_ADC_IN_GPIO5,   CY_ADCCOMP_ADC_IN_GPIO6,   CY_ADCCOMP_ADC_IN_GPIO7,   CY_ADCCOMP_ADC_IN_LHL_GPIO_2 = 0,   CY_ADCCOMP_ADC_IN_LHL_GPIO_3 = 1,   CY_ADCCOMP_ADC_IN_LHL_GPIO_4 = 2,   CY_ADCCOMP_ADC_IN_LHL_GPIO_5 = 3,   CY_ADCCOMP_ADC_IN_LHL_GPIO_6 = 4,   CY_ADCCOMP_ADC_IN_LHL_GPIO_7 = 5,   CY_ADCCOMP_ADC_IN_LHL_GPIO_8 = 6,   CY_ADCCOMP_ADC_IN_LHL_GPIO_9 = 7,   CY_ADCCOMP_ADC_IN_I_MIC = 8,   CY_ADCCOMP_ADC_IN_OPEN = 16 }
enum	cy_en_adccomp_lpcomp_negative_channel_t {   CY_ADCCOMP_LPCOMP_IN_N_GPIO04,   CY_ADCCOMP_LPCOMP_IN_N_GPIO15,   CY_ADCCOMP_LPCOMP_IN_N_OPEN = 4,   CY_ADCCOMP_LPCOMP_1_IN_N_LHL_GPIO_6 = 0,   CY_ADCCOMP_LPCOMP_1_IN_N_LHL_GPIO_7 = 1,   CY_ADCCOMP_LPCOMP_1_IN_N_OPEN = 4,   CY_ADCCOMP_LPCOMP_2_IN_N_LHL_GPIO_2 = 0,   CY_ADCCOMP_LPCOMP_2_IN_N_LHL_GPIO_3 = 1,   CY_ADCCOMP_LPCOMP_2_IN_N_OPEN = 4 }
enum	cy_en_adccomp_lpcomp_positive_channel_t {   CY_ADCCOMP_LPCOMP_IN_P_GPIO26,   CY_ADCCOMP_LPCOMP_IN_P_GPIO37,   CY_ADCCOMP_LPCOMP_IN_P_MIC,   CY_ADCCOMP_LPCOMP_IN_P_OPEN = 4,   CY_ADCCOMP_LPCOMP_1_IN_P_LHL_GPIO_8 = 0,   CY_ADCCOMP_LPCOMP_1_IN_P_LHL_GPIO_9 = 1,   CY_ADCCOMP_LPCOMP_1_IN_P_I_MIC = 2,   CY_ADCCOMP_LPCOMP_1_IN_P_OPEN = 4,   CY_ADCCOMP_LPCOMP_2_IN_P_LHL_GPIO_4 = 0,   CY_ADCCOMP_LPCOMP_2_IN_P_LHL_GPIO_5 = 1,   CY_ADCCOMP_LPCOMP_2_IN_P_I_MIC = 2,   CY_ADCCOMP_LPCOMP_2_IN_P_OPEN = 4 }
enum	cy_en_adccomp_lpcomp_hyst_t {   CY_ADCCOMP_LPCOMP_HYST_LIMIT_0MV_NONE,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_4MV_78DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_8MV_84DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_12MV_87_5DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_16MV_90DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_20MV_92DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_24MV_93_5DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_28MV_95DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_32MV_96DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_36MV_97DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_40MV_98DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_44MV_99DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_48MV_99_6DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_52MV_100_3DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_56MV_101DB,   CY_ADCCOMP_LPCOMP_HYST_LIMIT_60MV_101_5DB }
enum	cy_en_adccomp_adc_clk_in_pdm_out_t {   CY_ADCCOMP_ADC_CLK_IN_1MHZ_PDM_OUT_1MHZ,   CY_ADCCOMP_ADC_CLK_IN_2MHZ_PDM_OUT_1MHZ,   CY_ADCCOMP_ADC_CLK_IN_2MHZ_PDM_OUT_2MHZ,   CY_ADCCOMP_ADC_CLK_IN_4MHZ_PDM_OUT_2MHZ }
enum	cy_en_adccomp_status_t {   CY_ADCCOMP_SUCCESS = 0x00u,   CY_ADCCOMP_BAD_PARAM,   CY_ADCCOMP_CLOCK_REQ_FAIL,   CY_ADCCOMP_NOT_SUPPORTED }
	adc and low power comparator error codes. More...
enum	cy_adccomp_status_register_mask_t {   CY_ADCCOMP_STATUS_LPCOMP1_LATCHED_HIGH = (1 << 4),   CY_ADCCOMP_STATUS_LPCOMP2_LATCHED_HIGH = (1 << 5),   CY_ADCCOMP_STATUS_ADC_PDM_DATA_READY = (1 << 7),   CY_ADCCOMP_STATUS_ADC_GM_LDO_OK = (1 << 8),   CY_ADCCOMP_STATUS_ADC_TIMER_SET = (1 << 9),   CY_ADCCOMP_STATUS_ADC_CLK_READY = (1 << 11) }
enum	cy_en_adccomp_adc_pga_gain_ctrl_t {   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_0,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_1,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_2,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_3,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_4,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_5,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_6,   CY_ADCCOMP_ADC_PGA_GAIN_CTRL_7 }
enum	cy_en_adccomp_adc_mode_t {   CY_ADCCOMP_ADC_DC,   CY_ADCCOMP_ADC_MIC }

Enumeration Type Documentation

enum cy_en_adccomp_lpcomp_id_t

< ADCCOMP register configuration

< LPCOMP instances

Enumerator
CY_ADCCOMP_LPCOMP_1	LPCOMP instance 0.
CY_ADCCOMP_LPCOMP_2	LPCOMP instance 1.

enum cy_en_adccomp_lpcomp_mode_t

Enumerator
CY_ADCCOMP_LPCOMP_DC	DC mode: comparator assert when the V(+) - V(-) > 0.5*hysterisis limit.
CY_ADCCOMP_LPCOMP_NTD	NTD mode: comparator to detect when the peak-peak mic input level is larger than the selected hysterisis limit.

enum cy_en_adccomp_adc_dc_channel_t

Enumerator
CY_ADCCOMP_ADC_IN_GPIO0	ADC input channel for DC conversion. GPIO 0 DEPRECATED
CY_ADCCOMP_ADC_IN_GPIO1	GPIO 1 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO2	GPIO 2 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO3	GPIO 3 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO4	GPIO 4 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO5	GPIO 5 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO6	GPIO 6 DEPRECATED.
CY_ADCCOMP_ADC_IN_GPIO7	GPIO 7 DEPRECATED.
CY_ADCCOMP_ADC_IN_LHL_GPIO_2	GPIO 0.
CY_ADCCOMP_ADC_IN_LHL_GPIO_3	GPIO 1.
CY_ADCCOMP_ADC_IN_LHL_GPIO_4	GPIO 2.
CY_ADCCOMP_ADC_IN_LHL_GPIO_5	GPIO 3.
CY_ADCCOMP_ADC_IN_LHL_GPIO_6	GPIO 4.
CY_ADCCOMP_ADC_IN_LHL_GPIO_7	GPIO 5.
CY_ADCCOMP_ADC_IN_LHL_GPIO_8	GPIO 6.
CY_ADCCOMP_ADC_IN_LHL_GPIO_9	GPIO 7.
CY_ADCCOMP_ADC_IN_OPEN	input to ADC is open

enum cy_en_adccomp_lpcomp_negative_channel_t

Enumerator
CY_ADCCOMP_LPCOMP_IN_N_GPIO04	Comparator -ve terminal input MUX. GPIO0 to LPCOMP2 -ve terminal or GPIO4 to LPCOMP1 -ve terminal DEPRECATED
CY_ADCCOMP_LPCOMP_IN_N_GPIO15	GPIO1 to LPCOMP2 -ve terminal or GPIO5 to LPCOMP1 -ve terminal DEPRECATED.
CY_ADCCOMP_LPCOMP_IN_N_OPEN	LPCOMP negative terminal input to open.
CY_ADCCOMP_LPCOMP_1_IN_N_LHL_GPIO_6	Comparator 1's -ve terminal is LHL_GPIO_6.
CY_ADCCOMP_LPCOMP_1_IN_N_LHL_GPIO_7	Comparator 1's -ve terminal is LHL_GPIO_7.
CY_ADCCOMP_LPCOMP_1_IN_N_OPEN	comparator 1's negative terminal input to open
CY_ADCCOMP_LPCOMP_2_IN_N_LHL_GPIO_2	Comparator 2's -ve terminal is LHL_GPIO_2.
CY_ADCCOMP_LPCOMP_2_IN_N_LHL_GPIO_3	Comparator 2's -ve terminal is LHL_GPIO_3.
CY_ADCCOMP_LPCOMP_2_IN_N_OPEN	comparator 2's negative terminal input to open

enum cy_en_adccomp_lpcomp_positive_channel_t

Enumerator
CY_ADCCOMP_LPCOMP_IN_P_GPIO26	Comparator +ve terminal input MUX. GPIO2 to LPCOMP2 +ve terminal or GPIO6 to LPCOMP1 +ve terminal DEPRECATED
CY_ADCCOMP_LPCOMP_IN_P_GPIO37	GPIO3 to LPCOMP2 +ve terminal or GPIO7 to LPCOMP1 +ve terminal DEPRECATED.
CY_ADCCOMP_LPCOMP_IN_P_MIC	MIC input to positive terminal of comparator. Applicable only in NTD mode
CY_ADCCOMP_LPCOMP_IN_P_OPEN	LPCOMP positive terminal input to open.
CY_ADCCOMP_LPCOMP_1_IN_P_LHL_GPIO_8	Comparator 1's +ve terminal is LHL_GPIO_8.
CY_ADCCOMP_LPCOMP_1_IN_P_LHL_GPIO_9	Comparator 1's +ve terminal is LHL_GPIO_9.
CY_ADCCOMP_LPCOMP_1_IN_P_I_MIC	Comparator 1's +ve terminal is i_MIC.
CY_ADCCOMP_LPCOMP_1_IN_P_OPEN	Comparator 1's +ve terminal is open.
CY_ADCCOMP_LPCOMP_2_IN_P_LHL_GPIO_4	Comparator 1's +ve terminal is LHL_GPIO_4.
CY_ADCCOMP_LPCOMP_2_IN_P_LHL_GPIO_5	Comparator 2's +ve terminal is LHL_GPIO_5.
CY_ADCCOMP_LPCOMP_2_IN_P_I_MIC	Comparator 1's +ve terminal is i_MIC.
CY_ADCCOMP_LPCOMP_2_IN_P_OPEN	Comparator 1's +ve terminal is open.

enum cy_en_adccomp_adc_clk_in_pdm_out_t

Enumerator
CY_ADCCOMP_ADC_CLK_IN_1MHZ_PDM_OUT_1MHZ	Input to adc is 1 MHz and o/p PDM data required is 1 MHz.
CY_ADCCOMP_ADC_CLK_IN_2MHZ_PDM_OUT_1MHZ	Input to adc is 2 MHz and o/p PDM data required is 1 MHz.
CY_ADCCOMP_ADC_CLK_IN_2MHZ_PDM_OUT_2MHZ	Input to adc is 2 MHz and o/p PDM data required is 2 MHz.
CY_ADCCOMP_ADC_CLK_IN_4MHZ_PDM_OUT_2MHZ	Input to adc is 4 MHz and o/p PDM data required is 1 MHz.

enum cy_en_adccomp_status_t

adc and low power comparator error codes.

enum cy_adccomp_status_register_mask_t

Enumerator
CY_ADCCOMP_STATUS_LPCOMP1_LATCHED_HIGH	Comparator 1 o/p latched high.
CY_ADCCOMP_STATUS_LPCOMP2_LATCHED_HIGH	Comparator 2 o/p latched high.
CY_ADCCOMP_STATUS_ADC_PDM_DATA_READY	Reflects when ADC enabled and PDM data is ready.
CY_ADCCOMP_STATUS_ADC_GM_LDO_OK	i.e. After ADC internal LDO’s power-up sequence is completed.
CY_ADCCOMP_STATUS_ADC_TIMER_SET	i.e. When the ADC 100us timer is set.
CY_ADCCOMP_STATUS_ADC_CLK_READY	Indicates ADC input clock is a valid clock.

enum cy_en_adccomp_adc_pga_gain_ctrl_t

Enumerator
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_0	Gain 8/8, Max i/p(Vpp) = 1.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_1	Gain 8/7, Max i/p(Vpp) = 875 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_2	Gain 8/6, Max i/p(Vpp) = 750 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_3	Gain 8/5, Max i/p(Vpp) = 625 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_4	Gain 8/4, Max i/p(Vpp) = 500 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_5	Gain 8/3, Max i/p(Vpp) = 375 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_6	Gain 8/2, Max i/p(Vpp) = 250 m.
CY_ADCCOMP_ADC_PGA_GAIN_CTRL_7	Gain 8/1, Max i/p(Vpp) = 125 m.

enum cy_en_adccomp_adc_mode_t

Enumerator
CY_ADCCOMP_ADC_DC	DC voltage measurement.
CY_ADCCOMP_ADC_MIC	Analog MIC with PGA.