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CAT2 Peripheral Driver Library
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CAT2 Peripheral Driver Library
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Struct to hold the power parameters settings.
Data Fields | |
| uint8_t | fb_type |
| Type of power feedback: Bit 0 –> No feedback Bit 1 –> PWM Bit 2 –> Direct feedback Bit 3 –> Opto-isolator based feedback. | |
| uint8_t | reserved |
| Reserved area for future expansion. More... | |
| uint16_t | vbus_min_volt |
| VBus minimum voltage in mV. | |
| uint16_t | vbus_max_volt |
| VBus maximum voltage in mV. | |
| uint16_t | vbus_dflt_volt |
| Default VBus supply voltage when feedback control is tri-stated. More... | |
| uint16_t | cable_resistance |
| Cable resistance in mOhm. | |
| uint16_t | vbus_offset_volt |
| VBus offset voltage in addition to contracted voltage in mV. | |
| uint8_t | current_sense_res |
| Available to adjust CSA accuracy on board. More... | |
| uint8_t | src_gate_drv_str |
| Vbus source gate drive strength. More... | |
| uint16_t | vbtr_up_step_width |
| Vbtr Upward transition step width in 1us units. More... | |
| uint16_t | vbtr_down_step_width |
| Vbtr Downward transition step width in 1us units For single slope design, this shall be used for full voltage range. More... | |
| uint8_t | prim_sec_turns_ratio |
| Primary to secondary turns ratio rounded to nearest decimal. More... | |
| uint8_t | sr_enable |
| Enable/Disable the SR controller. | |
| uint8_t | sr_rise_time |
| SR gate driver rise time configuration. More... | |
| uint8_t | sr_fall_time |
| SR gate driver fall time configuration 0 -> Slow 1 -> Normal 2 -> Fast. | |
| uint8_t | sr_async_thresh |
| Secondary width below which GDRV will be gated. More... | |
| uint8_t | sr_supply_doubler |
| Enable/Disable the doubler for gate drive function. | |
| uint8_t | reserved_1 |
| Reserved for future use. | |
| uint8_t | buck_boost_operating_mode |
| Indicates mode of Buck-Boost regulation. More... | |
| uint8_t | pwm_mode |
| Indicates operational mode of power adapter secondary controller. | |
| uint8_t | pwm_min_freq |
| Minimum allowed switching frequency in QR/QR+FF mode in KHz. | |
| uint8_t | pwm_max_freq |
| Maximum allowed switching frequency in QR/QR+FF mode in KHz. | |
| uint8_t | pwm_fix_freq |
| PWM switching frequency in FF mode in KHz. | |
| uint8_t | max_pwm_duty_cycle |
| Maximum allowed PWM pulse duty cycle. | |
| uint8_t | min_pwm_duty_cycle |
| Minimum allowed PWM pulse duty cycle. | |
| uint8_t | pwm_gate_pull_up_drv_strnth_LS1 |
| adjust gate pull-up drive strength | |
| uint8_t | pwm_gate_pull_up_drv_strnth_LS2 |
| adjust gate pull-up drive strength | |
| uint8_t | pwm_gate_pull_up_drv_strnth_HS1 |
| adjust gate pull-up drive strength | |
| uint8_t | pwm_gate_pull_up_drv_strnth_HS2 |
| adjust gate pull-up drive strength | |
| uint8_t | pwm_dithering_type |
| enable / disable the dithering frequency configuration and pwm_dithering_type | |
| uint8_t | pwm_dithering_freq_range |
| % of frequency dithering based on the set switching frequency | |
| uint8_t | power_inductor_value |
| Inductance L required for slope_comp_control calculation. | |
| uint8_t | peak_current_sense_resistor |
| Ri required for slope_comp_control calculation. | |
| uint8_t | phase_angle_control |
| phase angle between ports in degrees | |
| uint8_t | peak_current_limit |
| Set the Current limit to shutdown the converter so that inductor shall not saturate. | |
| uint8_t | max_pwm_duty_cycle_high_line |
| Maximum allowed PWM pulse duty cycle for high line condition. | |
| uint8_t | reserved_2 |
| Reserved for future use. | |
| uint16_t | vbtr_up_step_width_below_5v |
| Vbtr Upward transition step width in 1us units for dual slope design when VBUS is below 5V. | |
| uint16_t | vbtr_down_step_width_below_5V |
| Vbtr Downward transition step width in 1us units for dual slope design when VBUS is below 5V. | |
| uint16_t | pwm_max_freq_ex |
| Maximum allowed switching frequency in QR/QR+FF mode in KHz, extended for more than 254kHz operation. More... | |
| uint8_t | pwm_gate_pull_down_drv_strnth_LS1 |
| adjust gate pull-down drive strength | |
| uint8_t | pwm_gate_pull_down_drv_strnth_LS2 |
| adjust gate pull-down drive strength | |
| uint8_t | pwm_gate_pull_down_drv_strnth_HS1 |
| adjust gate pull-down drive strength | |
| uint8_t | pwm_gate_pull_down_drv_strnth_HS2 |
| adjust gate pull-down drive strength | |
| uint8_t | bbclk_freq |
| Buck boost controller clock frequency in units of MHz. | |
| uint8_t | pwm_fix_freq_dith |
| Center PWM switching frequency when dithering is enabled. | |
| uint8_t | pwm_dith_spread_cycles |
| Number of BBCLK cycles of spread required to achieve configured range of frequency spread. | |
| uint8_t | reserved_3 [1] |
| Reserved for future use. | |
| uint16_t | bb_output_volt |
| Default buck-boost controller output voltage in mV. | |
| uint8_t cy_stc_buck_boost_cfg_t::reserved |
Reserved area for future expansion.
| uint16_t cy_stc_buck_boost_cfg_t::vbus_dflt_volt |
Default VBus supply voltage when feedback control is tri-stated.
| uint8_t cy_stc_buck_boost_cfg_t::current_sense_res |
Available to adjust CSA accuracy on board.
Unit of 0.1mOhm min_value = 10 max_value = 100
| uint8_t cy_stc_buck_boost_cfg_t::src_gate_drv_str |
Vbus source gate drive strength.
0 -> Slow 1 -> Normal 2 -> Fast
| uint16_t cy_stc_buck_boost_cfg_t::vbtr_up_step_width |
Vbtr Upward transition step width in 1us units.
For single slope design, this shall be used for full voltage range. For dual slope design this shall be used only for transitions above 5v.
| uint16_t cy_stc_buck_boost_cfg_t::vbtr_down_step_width |
Vbtr Downward transition step width in 1us units For single slope design, this shall be used for full voltage range.
For dual slope design this shall be used only for transitions above 5v.
| uint8_t cy_stc_buck_boost_cfg_t::prim_sec_turns_ratio |
Primary to secondary turns ratio rounded to nearest decimal.
min_value = 4 max_value = 10
| uint8_t cy_stc_buck_boost_cfg_t::sr_rise_time |
SR gate driver rise time configuration.
0 -> Slow 1 -> Normal 2 -> Fast
| uint8_t cy_stc_buck_boost_cfg_t::sr_async_thresh |
Secondary width below which GDRV will be gated.
Units in number of PASC Clock cycles.
| uint8_t cy_stc_buck_boost_cfg_t::buck_boost_operating_mode |
Indicates mode of Buck-Boost regulation.
| uint16_t cy_stc_buck_boost_cfg_t::pwm_max_freq_ex |
Maximum allowed switching frequency in QR/QR+FF mode in KHz, extended for more than 254kHz operation.