Startup (System Configuration Files)

Provides device startup, system configuration, and linker script files. More...

Modules
	Functions
	Global Variables

Detailed Description

Provides device startup, system configuration, and linker script files.

The system startup provides the followings features:

• Device Memory Definition
• Device Initialization
• Heap and Stack Configuration
• Default Interrupt Handlers Definition
• Vectors Table Copy from Flash to RAM

Configuration Considerations

Device Memory Definition

The flash and RAM allocation is defined by the linker scripts.

Note

The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see warnings during the build process. To eliminate build warnings in your project, you can simply comment out or remove the relevant code in the linker file.

ARM GCC
The flash and RAM sections for the CPU are defined in the linker file: for example, 'cy8c4xx5.ld'.

Change the flash and RAM sizes by editing the macros value in the linker file:

__FLASH_START = 0x00000000;
__FLASH_SIZE =  0x00008000;

__RAM_START = 0x20000000;
__RAM_SIZE =  0x00001000;

ARM MDK
The flash and RAM sections for the CPU are defined in the linker file: for example, 'cy8c4xx5.sct'.

Note

The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker file. In that case you may see the warnings during the build process: L6314W (no section matches pattern) and/or L6329W (pattern only matches removed unused sections). In your project, you can suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to the linker. You can also comment out or remove the relevant code in the linker file.

Change the flash and RAM sizes by editing the macros value in the linker file:

#define __FLASH_START  0x00000000
#define __FLASH_SIZE   0x00008000

#define __RAM_START    0x20000000
#define __RAM_SIZE     0x00001000

IAR
The flash and RAM sections for the CPU are defined in the linker files: for example, 'cy8c4xx5.icf'.

Change the flash and RAM sizes by editing the macros value in the linker file:

define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__   = 0x00007FFF;

define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM1_end__   = 0x20000FFF;

Device Initialization

After a power-on-reset (POR), the boot process is handled by the boot code from the on-chip ROM that is always executed by the core. The boot code passes the control to the startup code located in flash.

The startup code performs the device initialization by a call to Reset_Handler(), which calls SystemInit(), and then calls the CMSIS-defined __PROGRAM_START().

Heap and Stack Configuration

The heap and stack configurations are defined by the linker scripts.

By default, the stack size is set to 0x0000400 and the heap size is allocated dynamically to the whole available free memory up to stack memory and it is set to the 0x00000080 (for ARM GCC and IAR compilers) as minimal value.

Change the stack size by editing the macro value in the linker file: ARM GCC

__STACK_SIZE = 0x00000400;

Note

Correct operation of malloc and related functions depends on the working implementation of the 'sbrk' function. Newlib-nano (default C runtime library used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that doesn't check for heap and stack collisions during excessive memory allocations. To ensure the heap always remains within the range defined by __HeapBase and __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:

#include <stdlib.h>
#include <errno.h>

void * _sbrk(uint32_t incr)
{
    extern uint8_t __HeapBase, __HeapLimit;
    static uint8_t *heapBrk = &__HeapBase;
    uint8_t *prevBrk = heapBrk;
    if (incr > (uint32_t)(&__HeapLimit - heapBrk))
    {
        errno = ENOMEM;
        return (void *)-1;
    }
    heapBrk += incr;
    return prevBrk;
}

For FreeRTOS-enabled multi-threaded applications, it is sufficient to include clib-support library that provides newlib-compatible implementations of 'sbrk', '__malloc_lock' and '__malloc_unlock':
https://github.com/Infineon/clib-support.

ARM MDK

#define __STACK_SIZE       0x00000400

IAR

define symbol __ICFEDIT_size_cstack__ = 0x0400;

Default Interrupt Handlers Definition

The default interrupt handler functions are defined as weak functions to a dummy handler in the startup file. The naming convention for the interrupt handler names is <interrupt_name>_IRQHandler. A default interrupt handler can be overwritten in user code by defining the handler function using the same name. For example:

 void scb_0_interrupt_IRQHandler(void)
{
    ...
}

Vectors Table Copy from Flash to RAM

This process uses memory sections defined in the linker script. The vector table address (and the vector table itself) is defined in the startup files (e.g. startup_psoc4100sp.c). The code in these files defines the Reset_Handler, represents __VECTOR_TABLE as vector table in Flash and __RAM_VECTOR_TABLE represents this table in RAM.
The vector table is copied from Flash to RAM in Reset_Handler using memcpy().

memcpy(__RAM_VECTOR_TABLE, __VECTOR_TABLE, CY_VECTOR_TABLE_SIZE_BYTES);

Changelog

Version	Changes	Reason for Change
2.1	Added Cy_BootStatus() for PSoC4 HVMS/PA platform. Updated Reset_Handler() to support Default Handler for Boot-Up Status.	Major: Support for new devices.
	Updated SystemInit() function for PSoC4 HVMS/PA devices. Minor documentation updates.
2.0	Removed unused extern cy_delayFreqHz.	PDL major revision.
1.10.2	Update the paths to the code snippets.	PDL structure update.
1.10.1	Added support for PMG1S0, PMG1S1, PMG1S2, PMG1S3 devices.	New device support.
	Added missing __ICFEDIT_region symbols to the IAR linker scripts.	Improve ICF editor support.
1.10	Updated Reset_Handler() for Cortex-M0 devices.	Implementation and documentation enhancements.
	Updated Reset_Handler() with IAR compiler support.
	Added low-level initialization routine for the RTOS-enabled applications.
	Updated system header with the vector table allocation.
	Set default system core clock frequency to 24 MHz.
1.0	Initial version