Flash (Flash System Routine)

Internal Flash and Supervisory Flash memory programming. More...

Modules
	Macros
	Functions
	Enumerated Types

Detailed Description

Internal Flash and Supervisory Flash memory programming.

The functions and other declarations used in this driver are in cy_flash.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

Flash memory in PSOC devices provides non-volatile storage for the user firmware, user configuration data, and bulk data storage.

Flash programming operations are implemented as system calls. System calls are executed out of SROM in the privileged mode of operation. Users have no access to read or modify the SROM code. The CPU requests the system call by writing the function opcode and parameters to the System Performance Controller (SPC) input registers, and then requesting the SROM to execute the function. Based on the function opcode, the SPC executes the corresponding system call from SROM and updates the SPC status register. The CPU should read this status register for the pass/fail result of the function execution.

Note

Flash write operations modify the clock settings of the device during the period of the write operation. Refer to the Cy_Flash_WriteRow() documentation for details.

Configuration Considerations

Writing to Flash can take up to 20 milliseconds. During this time, the device should not be reset (including XRES pin, software reset, and watchdog) or unexpected changes may be made to portions of the Flash. Also, the low-voltage detect circuits should be configured to generate an interrupt instead of a reset.

The Flash can be read either by the cache controller or the SPC. Flash write can be performed only by the SPC. Both the SPC and cache cannot simultaneously access Flash memory. If the cache controller tries to access Flash at the same time as the SPC, then it must wait until the SPC completes its Flash access operation. The CPU, which accesses the Flash memory through the cache controller, is therefore also stalled in this circumstance. If a CPU code fetch has to be done from Flash memory due to a cache miss condition, then the cache would have to wait until the SPC completes the Flash write operation. Thus the CPU code execution will also be halted till the Flash write is complete. Flash is directly mapped into memory space and can be read directly.

More Information

See the technical reference manual (TRM) for more information about the Flash architecture.

Changelog

Version	Changes	Reason for Change
1.30	Added check for syscall completion .	Bug fix.
	Improved FLASH Macro number calculation.	Minor enhancement.
1.20	Enabled flash non-blocking write operations for devices with 1 flash array.	Minor enhancement.
1.10	Added Flash protection control support, Added ECC support.	New feature support.
	Added support for extra rows FLASH Macro.	Minor enhancement.
	Added support for latest FLASH page size macro.	Minor enhancement.
1.0.1	Removed unused library.	Minor enhancement.
1.0	Initial version