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MTB CAT1 Peripheral driver library
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MTB CAT1 Peripheral driver library
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PDM-PCM Test Mode configuration.
Data Fields | |
| uint8_t | drive_delay_hi |
| Interface drive delay on the high phase of the PDM interface clock. More... | |
| uint8_t | drive_delay_lo |
| Interface drive delay on the low phase of the PDM interface clock. More... | |
| uint8_t | mode_hi |
| Pattern generator mode on the high phase of the PDM interface clock. More... | |
| uint8_t | mode_lo |
| Pattern generator mode on the low phase of the PDM interface clock. More... | |
| uint8_t | audio_freq_div |
| Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. More... | |
| bool | enable |
| enable | |
| uint8_t cy_stc_test_config_t::drive_delay_hi |
Interface drive delay on the high phase of the PDM interface clock.
This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm
| uint8_t cy_stc_test_config_t::drive_delay_lo |
Interface drive delay on the low phase of the PDM interface clock.
This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm
| uint8_t cy_stc_test_config_t::mode_hi |
Pattern generator mode on the high phase of the PDM interface clock.
This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave
| uint8_t cy_stc_test_config_t::mode_lo |
Pattern generator mode on the low phase of the PDM interface clock.
This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave
| uint8_t cy_stc_test_config_t::audio_freq_div |
Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency.
This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below: Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV)