cy_stc_syspm_sdr_params_t Struct Reference

Description

The structure contains syspm SDR0/SDR1(Step Down Regulator) LDO configuration parameters.

Note

This structure is available for CAT1B devices.

Data Fields
uint8_t	coreBuckVoltSel
	Core Buck Voltage Select cy_en_syspm_core_buck_voltage_t.
uint8_t	coreBuckMode
	Core Buck Mode : 0x01 - Low Power Mode, 0x11 - High Power Mode(Low Ripple Mode)
uint8_t	coreBuckDpSlpVoltSel
	Deep Sleep Core Buck Voltage Select cy_en_syspm_core_buck_voltage_t.
uint8_t	coreBuckDpSlpMode
	Deep sleep Core Buck Mode : 0x01 - Low Power Mode, 0x11 - High Power Mode(Low Ripple Mode)
uint8_t	sdrVoltSel
	SDR Regulator Voltage Select cy_en_syspm_sdr_voltage_t.
uint8_t	sdr0DpSlpVoltSel
	SDR Regulator Voltage Select cy_en_syspm_sdr_voltage_t.
bool	sdr0Allowbypass
	Allow SDR bypass : true - Allow SDR to bypass false - SDR is not bypassed and will regulate.
bool	sdr1HwControl
	Allow SDR1 HW Control : true - sdr1Enable(bit: SDR1_ENABLE) is ignored, HW will control false - sdr1Enable(bit: SDR1_ENABLE) will control, HW control is ignored.
bool	sdr1Enable
	SDR1 Enable/Disable: true - SDR1 is enabled false - SDR1 is disabled.