cy_stc_syspm_backup_regs_t Struct Reference

Description

This internal structure stores non-retained registers in the system Deep Sleep power mode.

Note

This enum is available for CAT1A devices. On wakeup from system Deep Sleep, these registers are restored.

Data Fields
uint32_t	CY_SYSPM_UDB_UDBIF_BANK_CTL_REG
	UDB interface control register.
uint32_t	CY_SYSPM_UDB_BCTL_MDCLK_EN_REG
	UDB bank MDCLK_EN register.
uint32_t	CY_SYSPM_UDB_BCTL_MBCLK_EN_REG
	UDB bank MBCLK_EN register.
uint32_t	CY_SYSPM_UDB_BCTL_BOTSEL_L_REG
	UDB bank BOTSEL_L register.
uint32_t	CY_SYSPM_UDB_BCTL_BOTSEL_U_REG
	UDB bank BOTSEL_U register.
uint32_t	CY_SYSPM_UDB_BCTL_QCLK_EN0_REG
	UDB bank QCLK_EN0 register.
uint32_t	CY_SYSPM_UDB_BCTL_QCLK_EN1_REG
	UDB bank QCLK_EN1 register.
uint32_t	CY_SYSPM_UDB_BCTL_QCLK_EN2_REG
	UDB bank QCLK_EN2 register.
uint32_t	CY_SYSPM_CM0_CLOCK_CTL_REG
	CPUSS CM0+ clock control register.
uint32_t	CY_SYSPM_CM4_CLOCK_CTL_REG
	CPUSS CM4 clock control register.