MTB CAT1 Peripheral driver library
cy_stc_seglcd_config_t Struct Reference

Description

Configuration structure.

Data Fields

cy_en_seglcd_speed_t speed
 Speed mode selection, see: cy_en_seglcd_speed_t. More...
 
cy_en_seglcd_wave_t wave
 Waveform type configuration, see: cy_en_seglcd_wave_t. More...
 
cy_en_seglcd_drive_t drive
 Driving mode configuration, see: cy_en_seglcd_drive_t. More...
 
cy_en_seglcd_bias_t bias
 PWM bias selection, see: cy_en_seglcd_bias_t. More...
 
cy_en_seglcd_lsclk_t lsClk
 Low Speed Mode clock selection, see: cy_en_seglcd_lsclk_t. More...
 
uint8_t comNum
 The number of Common connections, the valid range is 2...16 however the maximum is dependent on PSoC device family - there could be limitation to 4 or 8 commons, see the device TRM.
 
uint8_t frRate
 The LCD frame rate, the valid range is 30...150.
 
uint8_t contrast
 The LCD contrast, the valid range is 0...100.
 
uint32_t clkFreq
 The LCD clock frequency (ignored for CY_SEGLCD_LSCLK_LF mode, or in CY_SEGLCD_SPEED_LOW mode for MXLCD_ver1), the valid range is 10000...100000000 (Hz)
 

Field Documentation

◆ speed

cy_en_seglcd_speed_t cy_stc_seglcd_config_t::speed

Speed mode selection, see: cy_en_seglcd_speed_t.

◆ wave

cy_en_seglcd_wave_t cy_stc_seglcd_config_t::wave

Waveform type configuration, see: cy_en_seglcd_wave_t.

◆ drive

cy_en_seglcd_drive_t cy_stc_seglcd_config_t::drive

Driving mode configuration, see: cy_en_seglcd_drive_t.

◆ bias

cy_en_seglcd_bias_t cy_stc_seglcd_config_t::bias

PWM bias selection, see: cy_en_seglcd_bias_t.

◆ lsClk

cy_en_seglcd_lsclk_t cy_stc_seglcd_config_t::lsClk

Low Speed Mode clock selection, see: cy_en_seglcd_lsclk_t.

This is effective for MXLCD_ver2, for MXLCD_ver1 it is ignored.