Description

UART configuration structure.

Data Fields
cy_en_scb_uart_mode_t	uartMode
	Specifies the UART's mode of operation.

uint32_t	oversample
	Oversample factor for UART. More...

uint32_t	dataWidth
	The width of UART data (valid range is 5 to 9)

bool	enableMsbFirst
	Enables the hardware to shift out data element MSB first; otherwise, LSB first.

cy_en_scb_uart_stop_bits_t	stopBits
	Specifies the number of stop bits in the UART transaction, in half-bit increments.

cy_en_scb_uart_parity_t	parity
	Configures the UART parity.

bool	enableInputFilter
	Enables a digital 3-tap median filter (2 out of 3 voting) to be applied to the input of the RX FIFO to filter glitches on the line (for IrDA, this parameter is ignored) More...

bool	dropOnParityError
	Enables the hardware to drop data in the RX FIFO when a parity error is detected.

bool	dropOnFrameError
	Enables the hardware to drop data in the RX FIFO when a frame error is detected.

bool	enableMutliProcessorMode
	Enables the UART operation in Multi-Processor mode which requires dataWidth to be 9 bits (the 9th bit is used to indicate address byte)

uint32_t	receiverAddress
	If Multi Processor mode is enabled, this is the address of the RX FIFO. More...

uint32_t	receiverAddressMask
	This is the address mask for the Multi Processor address. More...

bool	acceptAddrInFifo
	Enables the hardware to accept the matching address in the RX FIFO. More...

bool	irdaInvertRx
	Inverts the IrDA RX input.

bool	irdaEnableLowPowerReceiver
	Enables the low-power receive for IrDA mode. More...

bool	smartCardRetryOnNack
	Enables retransmission of the frame placed in the TX FIFO when NACK is received in SmartCard mode (for Standard and IrDA , this parameter is ignored)

bool	enableCts
	Enables the usage of the CTS input signal for the transmitter. More...

cy_en_scb_uart_polarity_t	ctsPolarity
	Sets the CTS Polarity.

uint32_t	rtsRxFifoLevel
	When the RX FIFO has fewer entries than rtsRxFifoLevel, the RTS signal is active (note to disable RTS, set this field to zero)

cy_en_scb_uart_polarity_t	rtsPolarity
	Sets the RTS Polarity.

uint32_t	breakWidth
	Specifies the number of bits to detect a break condition.

bool	breaklevel
	Specifies the low or high level pulse detection for break condition. More...

uint32_t	rxFifoTriggerLevel
	When there are more entries in the RX FIFO than this level the RX trigger output goes high. More...

uint32_t	rxFifoIntEnableMask
	The bits set in this mask allow the event to cause an interrupt (See UART RX FIFO status. for the set of constants)

uint32_t	txFifoTriggerLevel
	When there are fewer entries in the TX FIFO then this level the TX trigger output goes high. More...

uint32_t	txFifoIntEnableMask
	Bits set in this mask allows the event to cause an interrupt (See UART TX FIFO Statuses for the set of constants)

Field Documentation

◆ oversample

uint32_t cy_stc_scb_uart_config_t::oversample

Oversample factor for UART.

The UART baud rate is the SCB Clock frequency / oversample (valid range is 8-16).
For IrDA, the oversample is always 16, unless irdaEnableLowPowerReceiver is enabled. Then the oversample is reduced to the UART IRDA Low Power Oversample factors set.

◆ enableInputFilter

bool cy_stc_scb_uart_config_t::enableInputFilter

Enables a digital 3-tap median filter (2 out of 3 voting) to be applied to the input of the RX FIFO to filter glitches on the line (for IrDA, this parameter is ignored)

◆ receiverAddress

uint32_t cy_stc_scb_uart_config_t::receiverAddress

If Multi Processor mode is enabled, this is the address of the RX FIFO.

If the address matches, data is accepted into the FIFO. If it does not match, the data is ignored.

◆ receiverAddressMask

uint32_t cy_stc_scb_uart_config_t::receiverAddressMask

This is the address mask for the Multi Processor address.

1 indicates that the incoming address must match the corresponding bit in the slave address. A 0 in the mask indicates that the incoming address does not need to match.

◆ acceptAddrInFifo

bool cy_stc_scb_uart_config_t::acceptAddrInFifo

Enables the hardware to accept the matching address in the RX FIFO.

This is useful when the device supports more than one address.

◆ irdaEnableLowPowerReceiver

bool cy_stc_scb_uart_config_t::irdaEnableLowPowerReceiver

Enables the low-power receive for IrDA mode.

Note that the transmission must be disabled if this mode is enabled.

◆ enableCts

bool cy_stc_scb_uart_config_t::enableCts

Enables the usage of the CTS input signal for the transmitter.

The transmitter waits for CTS to be active before sending data

◆ breaklevel

bool cy_stc_scb_uart_config_t::breaklevel

Specifies the low or high level pulse detection for break condition.

Note: This parameter is available for CAT1B, CAT1C and CAT1D devices.

◆ rxFifoTriggerLevel

uint32_t cy_stc_scb_uart_config_t::rxFifoTriggerLevel

When there are more entries in the RX FIFO than this level the RX trigger output goes high.

This output can be connected to a DMA channel through a trigger mux. Also, it controls the CY_SCB_UART_RX_TRIGGER interrupt source.

◆ txFifoTriggerLevel

uint32_t cy_stc_scb_uart_config_t::txFifoTriggerLevel

When there are fewer entries in the TX FIFO then this level the TX trigger output goes high.

This output can be connected to a DMA channel through a trigger mux. Also, it controls CY_SCB_UART_TX_TRIGGER interrupt source.