MTB CAT1 Peripheral driver library
Medium Frequency Domain Clock

General Description

The Medium Frequency Domain Clock is present only in SRSS_ver1_3.

Consists of MFO - the Medium Frequency Oscillator, and CLK_MF - the Medium Frequency Clock divider. This clock chain is designed to source the LCD block in Deep Sleep mode, see cy_en_seglcd_lsclk_t.

API Reference

 Functions
 
 Enumerated Types