Macros to check SPI TX FIFO status returned by Cy_SCB_SPI_GetTxFifoStatus function or assign mask for Cy_SCB_SPI_ClearTxFifoStatus function.
Each SPI TX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.
Macros | |
#define | CY_SCB_SPI_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk) |
The number of entries in the TX FIFO is less than the TX FIFO trigger level value. | |
#define | CY_SCB_SPI_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk) |
The TX FIFO is not full, there is a space for more data. | |
#define | CY_SCB_SPI_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk) |
The TX FIFO is empty, note that there may still be data in the shift register. | |
#define | CY_SCB_SPI_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk) |
An attempt to write to the full TX FIFO. | |
#define | CY_SCB_SPI_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk) |
Applicable only for the slave mode. More... | |
#define CY_SCB_SPI_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk) |
Applicable only for the slave mode.
The master tried to read more data elements than available.