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MTB CAT1 Peripheral driver library
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MTB CAT1 Peripheral driver library
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Macros to check I2C events passed by cy_cb_scb_i2c_handle_events_t callback.
Each event is encoded in a separate bit, and therefore it is possible to notify about multiple events.
Macros | |
| #define | CY_SCB_I2C_SLAVE_READ_EVENT (0x00000001UL) |
| Indicates that the slave was addressed and the master wants to read data. More... | |
| #define | CY_SCB_I2C_SLAVE_WRITE_EVENT (0x00000002UL) |
| Indicates that the slave was addressed and the master wants to write data. More... | |
| #define | CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT (0x00000004UL) |
| All slave data from the configured Read buffer has been loaded into the TX FIFO. More... | |
| #define | CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT (0x00000008UL) |
| The master has read all data out of the configured Read buffer. More... | |
| #define | CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT (0x00000010UL) |
| Indicates the master completed reading from the slave (set by the master NAK or Stop) | |
| #define | CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT (0x00000020UL) |
| Indicates the master completed writing to the slave (set by the master Stop or Restart) | |
| #define | CY_SCB_I2C_SLAVE_ERR_EVENT (0x00000040UL) |
| Indicates the I2C hardware detected an error. More... | |
| #define | CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT (0x00010000UL) |
| All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO. More... | |
| #define | CY_SCB_I2C_MASTER_WR_CMPLT_EVENT (0x00020000UL) |
| The master write started by Cy_SCB_I2C_MasterWrite is complete. | |
| #define | CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL) |
| The master read started by Cy_SCB_I2C_MasterRead is complete. | |
| #define | CY_SCB_I2C_MASTER_ERR_EVENT (0x00080000UL) |
| Indicates the I2C hardware has detected an error. More... | |
| #define CY_SCB_I2C_SLAVE_READ_EVENT (0x00000001UL) |
Indicates that the slave was addressed and the master wants to read data.
This event can be used to configure the slave Read buffer.
| #define CY_SCB_I2C_SLAVE_WRITE_EVENT (0x00000002UL) |
Indicates that the slave was addressed and the master wants to write data.
This event can be used to configure the slave Write buffer.
| #define CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT (0x00000004UL) |
All slave data from the configured Read buffer has been loaded into the TX FIFO.
The content of the Read buffer can be modified. Applicable only if the TX FIFO is used.
| #define CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT (0x00000008UL) |
The master has read all data out of the configured Read buffer.
This event can be used to configure the next Read buffer. If the buffer remains empty, the CY_SCB_I2C_DEFAULT_TX bytes are returned to the master.
| #define CY_SCB_I2C_SLAVE_ERR_EVENT (0x00000040UL) |
Indicates the I2C hardware detected an error.
Check Cy_SCB_I2C_SlaveGetStatus to determine the source of the error.
| #define CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT (0x00010000UL) |
All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO.
The content of the master write buffer can be modified. Applicable only if the TX FIFO is used.
| #define CY_SCB_I2C_MASTER_ERR_EVENT (0x00080000UL) |
Indicates the I2C hardware has detected an error.
It occurs together with CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or CY_SCB_I2C_MASTER_WR_CMPLT_EVENT depends on the direction of the transfer. Check Cy_SCB_I2C_MasterGetStatus to determine the source of the error.