Interrupt Masks

General Description

Macros
#define	CY_PDM_PCM_INTR_RX_TRIGGER   (PDM_INTR_RX_TRIGGER_Msk)
	Bit 16: More entries in the RX FIFO than specified by Trigger Level. More...
#define	CY_PDM_PCM_INTR_RX_NOT_EMPTY   (PDM_INTR_RX_NOT_EMPTY_Msk)
	Bit 18: RX FIFO is not empty. More...
#define	CY_PDM_PCM_INTR_RX_OVERFLOW   (PDM_INTR_RX_OVERFLOW_Msk)
	Bit 21: Attempt to write to a full RX FIFO. More...
#define	CY_PDM_PCM_INTR_RX_UNDERFLOW   (PDM_INTR_RX_UNDERFLOW_Msk)
	Bit 22: Attempt to read from an empty RX FIFO. More...

Macro Definition Documentation

CY_PDM_PCM_INTR_RX_TRIGGER

#define CY_PDM_PCM_INTR_RX_TRIGGER   (PDM_INTR_RX_TRIGGER_Msk)

Bit 16: More entries in the RX FIFO than specified by Trigger Level.

CY_PDM_PCM_INTR_RX_NOT_EMPTY

#define CY_PDM_PCM_INTR_RX_NOT_EMPTY   (PDM_INTR_RX_NOT_EMPTY_Msk)

Bit 18: RX FIFO is not empty.

CY_PDM_PCM_INTR_RX_OVERFLOW

#define CY_PDM_PCM_INTR_RX_OVERFLOW   (PDM_INTR_RX_OVERFLOW_Msk)

Bit 21: Attempt to write to a full RX FIFO.

CY_PDM_PCM_INTR_RX_UNDERFLOW

#define CY_PDM_PCM_INTR_RX_UNDERFLOW   (PDM_INTR_RX_UNDERFLOW_Msk)

Bit 22: Attempt to read from an empty RX FIFO.