MTB CAT1 Peripheral driver library

General Description

Enumerations

enum  cy_en_ms_ctl_status_t {
  CY_MS_CTL_SUCCESS = 0x00U,
  CY_MS_CTL_BAD_PARAM = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x01U,
  CY_MS_CTL_INVALID_STATE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x02U,
  CY_MS_CTL_FAILURE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x03U,
  CY_MS_CTL_UNAVAILABLE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x04U
}
 MSC API return status. More...
 
enum  en_ms_ctl_master_t {
  CPUSS_MS_ID_CM33_0 = 0,
  CPUSS_MS_ID_CM33_1 = 1,
  CPUSS_MS_ID_DMAC0_MS = 2,
  CPUSS_MS_ID_DMAC1_MS = 3,
  CPUSS_MS_ID_DW0 = 4,
  CPUSS_MS_ID_DW1 = 5,
  CPUSS_MS_ID_CODE_MS_0 = 6,
  CPUSS_MS_ID_SYS_MS_0 = 7,
  CPUSS_MS_ID_SYS_MS_1 = 8,
  CPUSS_MS_ID_EXP_MS_0 = 9,
  CPUSS_MS_ID_EXP_MS_1 = 10,
  CPUSS_MS_ID_EXP_MS_2 = 11,
  CPUSS_MS_ID_EXP_MS_3 = 12,
  CPUSS_MS_ID_EXP_MS_4 = 13,
  CPUSS_MS_ID_EXP_MS_5 = 14,
  CPUSS_MS_ID_EXP_MS_6 = 15,
  CPUSS_MS_ID_EXP_MS_7 = 16,
  CPUSS_MS_ID_SYS_MS_0_NVM = 17,
  CPUSS_MS_ID_SYS_MS_1_NVM = 18,
  CPUSS_MS_ID_TC_MS = 31
}
 Bus masters.
 
enum  en_ms_ctl_master_sc_acg_t {
  CODE_MS0_MSC = 0,
  SYS_MS0_MSC = 1,
  SYS_MS1_MSC = 2,
  EXP_MS_MSC = 3,
  DMAC0_MSC = 4,
  DMAC1_MSC = 5
}
 Bus masters security controller and ACG config.
 
enum  cy_en_ms_ctl_cfg_gate_resp_t {
  CY_MS_CTL_GATE_RESP_WAITED_TRFR = 0,
  CY_MS_CTL_GATE_RESP_ERR = 1
}
 Response type when ACG blocks incoming transfers. More...
 
enum  cy_en_ms_ctl_sec_resp_t {
  CY_MS_CTL_SEC_RESP_RAZ_WI = 0,
  CY_MS_CTL_SEC_RESP_ERR = 1
}
 Response type when MSC blocks transfers. More...
 
enum  cy_en_prot_pcmask_t {
  CY_MS_CTL_PCMASK0 = 0x0001U,
  CY_MS_CTL_PCMASK1 = 0x0002U,
  CY_MS_CTL_PCMASK2 = 0x0004U,
  CY_MS_CTL_PCMASK3 = 0x0008U,
  CY_MS_CTL_PCMASK4 = 0x0010U,
  CY_MS_CTL_PCMASK5 = 0x0020U,
  CY_MS_CTL_PCMASK6 = 0x0040U,
  CY_MS_CTL_PCMASK7 = 0x0080U,
  CY_MS_CTL_PCMASK8 = 0x0100U,
  CY_MS_CTL_PCMASK9 = 0x0200U,
  CY_MS_CTL_PCMASK10 = 0x0400U,
  CY_MS_CTL_PCMASK11 = 0x0800U,
  CY_MS_CTL_PCMASK12 = 0x1000U,
  CY_MS_CTL_PCMASK13 = 0x2000U,
  CY_MS_CTL_PCMASK14 = 0x4000U,
  CY_MS_CTL_PCMASK15 = 0x8000U,
  CY_PROT_PCMASK1 = 0x0001U,
  CY_PROT_PCMASK2 = 0x0002U,
  CY_PROT_PCMASK3 = 0x0004U,
  CY_PROT_PCMASK4 = 0x0008U,
  CY_PROT_PCMASK5 = 0x0010U,
  CY_PROT_PCMASK6 = 0x0020U,
  CY_PROT_PCMASK7 = 0x0040U,
  CY_PROT_PCMASK8 = 0x0080U,
  CY_PROT_PCMASK9 = 0x0100U,
  CY_PROT_PCMASK10 = 0x0200U,
  CY_PROT_PCMASK11 = 0x0400U,
  CY_PROT_PCMASK12 = 0x0800U,
  CY_PROT_PCMASK13 = 0x1000U,
  CY_PROT_PCMASK14 = 0x2000U,
  CY_PROT_PCMASK15 = 0x4000U
}
 Protection context mask (PC_MASK) More...
 

Enumeration Type Documentation

◆ cy_en_ms_ctl_status_t

MSC API return status.

Enumerator
CY_MS_CTL_SUCCESS 

Returned successful.

CY_MS_CTL_BAD_PARAM 

Bad parameter was passed.

CY_MS_CTL_INVALID_STATE 

The operation is not setup.

CY_MS_CTL_FAILURE 

The resource is locked.

CY_MS_CTL_UNAVAILABLE 

The resource is unavailable.

◆ cy_en_ms_ctl_cfg_gate_resp_t

Response type when ACG blocks incoming transfers.

Enumerator
CY_MS_CTL_GATE_RESP_WAITED_TRFR 

Waited transfer.

CY_MS_CTL_GATE_RESP_ERR 

Error response.

◆ cy_en_ms_ctl_sec_resp_t

Response type when MSC blocks transfers.

Enumerator
CY_MS_CTL_SEC_RESP_RAZ_WI 

Read as zero and write ignored.

CY_MS_CTL_SEC_RESP_ERR 

Error response.

◆ cy_en_prot_pcmask_t

Protection context mask (PC_MASK)

Enumerator
CY_MS_CTL_PCMASK0 

Mask to allow PC = 0.

CY_MS_CTL_PCMASK1 

Mask to allow PC = 1.

CY_MS_CTL_PCMASK2 

Mask to allow PC = 2.

CY_MS_CTL_PCMASK3 

Mask to allow PC = 3.

CY_MS_CTL_PCMASK4 

Mask to allow PC = 4.

CY_MS_CTL_PCMASK5 

Mask to allow PC = 5.

CY_MS_CTL_PCMASK6 

Mask to allow PC = 6.

CY_MS_CTL_PCMASK7 

Mask to allow PC = 7.

CY_MS_CTL_PCMASK8 

Mask to allow PC = 8.

CY_MS_CTL_PCMASK9 

Mask to allow PC = 9.

CY_MS_CTL_PCMASK10 

Mask to allow PC = 10.

CY_MS_CTL_PCMASK11 

Mask to allow PC = 11.

CY_MS_CTL_PCMASK12 

Mask to allow PC = 12.

CY_MS_CTL_PCMASK13 

Mask to allow PC = 13.

CY_MS_CTL_PCMASK14 

Mask to allow PC = 14.

CY_MS_CTL_PCMASK15 

Mask to allow PC = 15.

CY_PROT_PCMASK1 

Mask to allow PC = 1.

CY_PROT_PCMASK2 

Mask to allow PC = 2.

CY_PROT_PCMASK3 

Mask to allow PC = 3.

CY_PROT_PCMASK4 

Mask to allow PC = 4.

CY_PROT_PCMASK5 

Mask to allow PC = 5.

CY_PROT_PCMASK6 

Mask to allow PC = 6.

CY_PROT_PCMASK7 

Mask to allow PC = 7.

CY_PROT_PCMASK8 

Mask to allow PC = 8.

CY_PROT_PCMASK9 

Mask to allow PC = 9.

CY_PROT_PCMASK10 

Mask to allow PC = 10.

CY_PROT_PCMASK11 

Mask to allow PC = 11.

CY_PROT_PCMASK12 

Mask to allow PC = 12.

CY_PROT_PCMASK13 

Mask to allow PC = 13.

CY_PROT_PCMASK14 

Mask to allow PC = 14.

CY_PROT_PCMASK15 

Mask to allow PC = 15.