Features
The CAT5 ADC supports the following features:
- Resolution: 15 bit
- Input range from 0V to 1V
- Sample rate: Fixed 4096 ksps
- Minimum acquisition time: Up to 244 ns
- SW-based async transfer only (DMA is not supported)
- VREF: CYHAL_ADC_REF_INTERNAL (0.5V) only
- Single ended vneg: CYHAL_ADC_VNEG_VSSA
- Programmable gains of 8/8, 8/7, 8/4, 8/1
- DC measurement through 8 pins
- ADC Mic audio through MIC_P pin to the PDM-PCM
The following functions are not supported:
- Differential channels
- Continuous scanning
- Averaging. In cyhal_adc_config_t, average count must be 1 and average_mode_flags must be 0. In cyhal_adc_channel_config_t, enable_averaging must be false.
- External vref and bypass pins
There are 8 power gain amplifier (PGA) levels in the hardware. These are truncated to the 3 levels suported by the HAL. The default power is set to maximum gain. To control the gain, use cyhal_adc_set_power.
