The CAT2 (PSoC™ 4) I2S only supports TX in master mode.

There are no trigger connections available from the I2S peripheral to other peripherals on the CAT2 platform. Hence, the cyhal_i2s_enable_output and cyhal_i2s_disable_output are not supported on this platform.

It supports the following values for word lengths:

8 bits
16 bits
18 bits
20 bits
24 bits
32 bits

The channel length must be greater than or equal to the word length. On CAT2 devices, the set of supported channel lengths is the same as the set of supported word lengths.

The sclk signal is formed by integer division of the input clock source (either internally provided or from the mclk pin). The CAT2 I2S supports sclk divider values from 1 to 64.

Note: If the I2S hardware is initialized with a configurator-generated configuration via the cyhal_i2s_init_cfg function, the CYHAL_I2S_TX_HALF_EMPTY event will be raised at the configurator defined TX FIFO trigger level instead of the usual trigger level of half the FIFO depth.