Description

DSI Registers (GFXSS_MIPIDSI_DWCMIPIDSI)

Data Fields
__IM uint32_t	VERSION

__IOM uint32_t	PWR_UP

__IOM uint32_t	CLKMGR_CFG

__IOM uint32_t	DPI_VCID

__IOM uint32_t	DPI_COLOR_CODING

__IOM uint32_t	DPI_CFG_POL

__IOM uint32_t	DPI_LP_CMD_TIM

__IOM uint32_t	DBI_VCID

__IOM uint32_t	DBI_CFG

__IOM uint32_t	DBI_PARTITIONING_EN

__IOM uint32_t	DBI_CMDSIZE

__IOM uint32_t	PCKHDL_CFG

__IOM uint32_t	GEN_VCID

__IOM uint32_t	MODE_CFG

__IOM uint32_t	VID_MODE_CFG

__IOM uint32_t	VID_PKT_SIZE

__IOM uint32_t	VID_NUM_CHUNKS

__IOM uint32_t	VID_NULL_SIZE

__IOM uint32_t	VID_HSA_TIME

__IOM uint32_t	VID_HBP_TIME

__IOM uint32_t	VID_HLINE_TIME

__IOM uint32_t	VID_VSA_LINES

__IOM uint32_t	VID_VBP_LINES

__IOM uint32_t	VID_VFP_LINES

__IOM uint32_t	VID_VACTIVE_LINES

__IM uint32_t	RESERVED

__IOM uint32_t	CMD_MODE_CFG

__IOM uint32_t	GEN_HDR

__IOM uint32_t	GEN_PLD_DATA

__IM uint32_t	CMD_PKT_STATUS

__IOM uint32_t	TO_CNT_CFG

__IOM uint32_t	HS_RD_TO_CNT

__IOM uint32_t	LP_RD_TO_CNT

__IOM uint32_t	HS_WR_TO_CNT

__IOM uint32_t	LP_WR_TO_CNT

__IOM uint32_t	BTA_TO_CNT

__IOM uint32_t	SDF_3D

__IOM uint32_t	LPCLK_CTRL

__IOM uint32_t	PHY_TMR_LPCLK_CFG

__IOM uint32_t	PHY_TMR_CFG

__IOM uint32_t	PHY_RSTZ

__IOM uint32_t	PHY_IF_CFG

__IOM uint32_t	PHY_ULPS_CTRL

__IOM uint32_t	PHY_TX_TRIGGERS

__IM uint32_t	PHY_STATUS

__IOM uint32_t	PHY_TST_CTRL0

__IOM uint32_t	PHY_TST_CTRL1

__IM uint32_t	INT_ST0

__IM uint32_t	INT_ST1

__IOM uint32_t	INT_MSK0

__IOM uint32_t	INT_MSK1

__IOM uint32_t	PHY_CAL

__IM uint32_t	RESERVED1 [2]

__IOM uint32_t	INT_FORCE0

__IOM uint32_t	INT_FORCE1

__IM uint32_t	RESERVED2 [4]

__IOM uint32_t	DSC_PARAMETER

__IOM uint32_t	PHY_TMR_RD_CFG

__IM uint32_t	RESERVED3 [2]

__IOM uint32_t	VID_SHADOW_CTRL

__IM uint32_t	RESERVED4 [2]

__IM uint32_t	DPI_VCID_ACT

__IM uint32_t	DPI_COLOR_CODING_ACT

__IM uint32_t	RESERVED5

__IM uint32_t	DPI_LP_CMD_TIM_ACT

__IM uint32_t	RESERVED6 [7]

__IM uint32_t	VID_MODE_CFG_ACT

__IM uint32_t	VID_PKT_SIZE_ACT

__IM uint32_t	VID_NUM_CHUNKS_ACT

__IM uint32_t	VID_NULL_SIZE_ACT

__IM uint32_t	VID_HSA_TIME_ACT

__IM uint32_t	VID_HBP_TIME_ACT

__IM uint32_t	VID_HLINE_TIME_ACT

__IM uint32_t	VID_VSA_LINES_ACT

__IM uint32_t	VID_VBP_LINES_ACT

__IM uint32_t	VID_VFP_LINES_ACT

__IM uint32_t	VID_VACTIVE_LINES_ACT

__IM uint32_t	RESERVED7

__IM uint32_t	VID_PKT_STATUS

__IM uint32_t	RESERVED8 [9]

__IM uint32_t	SDF_3D_ACT

__IM uint32_t	RESERVED9 [923]

Field Documentation

◆ VERSION

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VERSION

0x00000000 Contains the version of the DSI host controller.

◆ PWR_UP

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PWR_UP

0x00000004 Controls the power up of the controller.

◆ CLKMGR_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::CLKMGR_CFG

0x00000008 Configures the factor for internal dividers to divide lanebyteclk for timeout purposes.

◆ DPI_VCID

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_VCID

0x0000000C Configures the Virtual Channel ID for DPI traffic.

◆ DPI_COLOR_CODING

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_COLOR_CODING

0x00000010 Configures DPI color coding.

◆ DPI_CFG_POL

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_CFG_POL

0x00000014 Configures the polarity of DPI signals.

◆ DPI_LP_CMD_TIM

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_LP_CMD_TIM

0x00000018 Configures the timing for low-power commands sent while in video mode.

◆ DBI_VCID

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DBI_VCID

0x0000001C Configures Virtual Channel ID for DBI traffic.

◆ DBI_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DBI_CFG

0x00000020 Configures the bit width of pixels for DBI.

◆ DBI_PARTITIONING_EN

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DBI_PARTITIONING_EN

0x00000024 Configures whether DWC_mipi_dsi_host is to partition DBI traffic automatically.

◆ DBI_CMDSIZE

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DBI_CMDSIZE

0x00000028 Configures the command size and the size for automatic partitioning of DBI packets.

◆ PCKHDL_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PCKHDL_CFG

0x0000002C Configures how EoTp, BTA, CRC and ECC are to be used, to meet peripherals characteristics

◆ GEN_VCID

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::GEN_VCID

0x00000030 Configures the Virtual Channel ID of READ responses to store and return to Generic interface.

◆ MODE_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::MODE_CFG

0x00000034 Configures the mode of operation between Video or Command Mode. (Commands can still be sent while in video mode.)

◆ VID_MODE_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_MODE_CFG

0x00000038 Configures several aspects of Video mode operation, the transmission mode, switching to low-power in the middle of a frame, enabling acknowledge and whether to send commands in low-power.

◆ VID_PKT_SIZE

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_PKT_SIZE

0x0000003C Configures the video packet size.

◆ VID_NUM_CHUNKS

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_NUM_CHUNKS

0x00000040 Configures the number of chunks to use. The data in each chunk has the size provided by VID_PKT_SIZE.

◆ VID_NULL_SIZE

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_NULL_SIZE

0x00000044 Configures the size of null packets.

◆ VID_HSA_TIME

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HSA_TIME

0x00000048 Configures the video HSA time.

◆ VID_HBP_TIME

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HBP_TIME

0x0000004C Configures the video HBP time.

◆ VID_HLINE_TIME

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HLINE_TIME

0x00000050 Configures the overall time for each video line.

◆ VID_VSA_LINES

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VSA_LINES

0x00000054 Configures the VSA period.

◆ VID_VBP_LINES

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VBP_LINES

0x00000058 Configures the VBP period.

◆ VID_VFP_LINES

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VFP_LINES

0x0000005C Configures the VFP period.

◆ VID_VACTIVE_LINES

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VACTIVE_LINES

0x00000060 Configures the vertical resolution of video.

◆ RESERVED

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED

◆ CMD_MODE_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::CMD_MODE_CFG

0x00000068 Configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands.

◆ GEN_HDR

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::GEN_HDR

0x0000006C Sets the header for new packets sent using the Generic interface.

◆ GEN_PLD_DATA

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::GEN_PLD_DATA

0x00000070 Sets the payload for packets sent using the Generic interface and, when read returns the contents of READ responses from the peripheral.

◆ CMD_PKT_STATUS

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::CMD_PKT_STATUS

0x00000074 Contains information about the status of FIFOs related to DBI and Generic interface.

◆ TO_CNT_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::TO_CNT_CFG

0x00000078 Configures counters that trigger timeout errors. These are used to warn the system of a failure, through an interrupt, and restart the controller in case of unexpected situations that cause deadlock conditions.

◆ HS_RD_TO_CNT

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::HS_RD_TO_CNT

0x0000007C Configures the Peripheral Response timeout after high-speed Read operations.

◆ LP_RD_TO_CNT

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::LP_RD_TO_CNT

0x00000080 Configures the Peripheral Response timeout after low-power Read operations.

◆ HS_WR_TO_CNT

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::HS_WR_TO_CNT

0x00000084 Configures the Peripheral Response timeout after high-speed Write operations.

◆ LP_WR_TO_CNT

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::LP_WR_TO_CNT

0x00000088 Configures the Peripheral Response timeout after low-power Write operations.

◆ BTA_TO_CNT

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::BTA_TO_CNT

0x0000008C Configures the Peripheral Response timeout after Bus Turnaround completion.

◆ SDF_3D

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::SDF_3D

0x00000090 Stores 3D control information for VSS packets in video mode.

◆ LPCLK_CTRL

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::LPCLK_CTRL

0x00000094 Configures the possibility for using non continuous clock in the clock lane.

◆ PHY_TMR_LPCLK_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TMR_LPCLK_CFG

0x00000098 Sets the time that DWC_mipi_dsi_host assumes in calculations for the clock lane to switch between high-speed and low-power.

◆ PHY_TMR_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TMR_CFG

0x0000009C Sets the time that DWC_mipi_dsi_host assumes in calculations for the data lanes to switch between high-speed and low-power.

◆ PHY_RSTZ

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_RSTZ

0x000000A0 Controls resets and the PLL of the D-PHY.

◆ PHY_IF_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_IF_CFG

0x000000A4 Configures the number of active lanes and the minimum time to remain in stop state.

◆ PHY_ULPS_CTRL

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_ULPS_CTRL

0x000000A8 Configures entering and leaving ULPS in the D-PHY.

◆ PHY_TX_TRIGGERS

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TX_TRIGGERS

0x000000AC Configures the pins that activate triggers in the D-PHY.

◆ PHY_STATUS

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_STATUS

0x000000B0 Contains information about the status of the D-PHY.

◆ PHY_TST_CTRL0

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TST_CTRL0

0x000000B4 Controls clock and clear pins of the D-PHY vendor specific interface.

◆ PHY_TST_CTRL1

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TST_CTRL1

0x000000B8 Controls data and enable pins of the D-PHY vendor specific interface.

◆ INT_ST0

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_ST0

0x000000BC Contains the status of interrupt sources from acknowledge reports and the D-PHY.

◆ INT_ST1

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_ST1

0x000000C0 Contains the status of interrupt sources related to timeouts, ECC, CRC, packet size, EoTp, Generic and DBI interfaces.

◆ INT_MSK0

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_MSK0

0x000000C4 Configures masks for the sources of interrupts that affect the INT_ST0 register. Write 1 to un-mask each error report.

◆ INT_MSK1

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_MSK1

0x000000C8 Configures masks for the sources of interrupts that affect the INT_ST1 register.

◆ PHY_CAL

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_CAL

0x000000CC Controls the skew calibration of D-PHY.

◆ RESERVED1

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED1[2]

◆ INT_FORCE0

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_FORCE0

0x000000D8 Forces interrupt that affect the INT_ST0 register.

◆ INT_FORCE1

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::INT_FORCE1

0x000000DC Forces interrupts that affect the INT_ST1 register.

◆ RESERVED2

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED2[4]

◆ DSC_PARAMETER

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DSC_PARAMETER

0x000000F0 Configures Display Stream Compression.

◆ PHY_TMR_RD_CFG

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::PHY_TMR_RD_CFG

0x000000F4 Configures times related to PHY to perform some operations in lane byte clock cycles.

◆ RESERVED3

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED3[2]

◆ VID_SHADOW_CTRL

__IOM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_SHADOW_CTRL

0x00000100 Controls dpi shadow feature

◆ RESERVED4

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED4[2]

◆ DPI_VCID_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_VCID_ACT

0x0000010C Holds the value that controller is using for DPI_VCID.

◆ DPI_COLOR_CODING_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_COLOR_CODING_ACT

0x00000110 Holds the value that controller is using for DPI_COLOR_CODING.

◆ RESERVED5

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED5

◆ DPI_LP_CMD_TIM_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::DPI_LP_CMD_TIM_ACT

0x00000118 Holds the value that controller is using for DPI_LP_CMD_TIM.

◆ RESERVED6

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED6[7]

◆ VID_MODE_CFG_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_MODE_CFG_ACT

0x00000138 Holds the value that controller is using for VID_MODE_CFG.

◆ VID_PKT_SIZE_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_PKT_SIZE_ACT

0x0000013C Holds the value that controller is using for VID_PKT_SIZE.

◆ VID_NUM_CHUNKS_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_NUM_CHUNKS_ACT

0x00000140 This register holds the value that controller is using for VID_NUM_CHUNKS.

◆ VID_NULL_SIZE_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_NULL_SIZE_ACT

0x00000144 Holds the value that controller is using for VID_NULL_SIZE.

◆ VID_HSA_TIME_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HSA_TIME_ACT

0x00000148 Holds the value that controller is using for VID_HSA_TIME.

◆ VID_HBP_TIME_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HBP_TIME_ACT

0x0000014C Holds the value that controller is using for VID_HBP_TIME.

◆ VID_HLINE_TIME_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_HLINE_TIME_ACT

0x00000150 Holds the value that controller is using for VID_HLINE_TIME.

◆ VID_VSA_LINES_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VSA_LINES_ACT

0x00000154 Holds the value that controller is using for VID_VSA_LINES.

◆ VID_VBP_LINES_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VBP_LINES_ACT

0x00000158 Holds the value that controller is using for VID_VBP_LINES.

◆ VID_VFP_LINES_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VFP_LINES_ACT

0x0000015C Holds the value that controller is using for VID_VFP_LINES.

◆ VID_VACTIVE_LINES_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_VACTIVE_LINES_ACT

0x00000160 Holds the value that controller is using for VID_VACTIVE_LINES.

◆ RESERVED7

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED7

◆ VID_PKT_STATUS

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::VID_PKT_STATUS

0x00000168 Contains information about the status of FIFOs related to DPI and eDPI interfaces.

◆ RESERVED8

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED8[9]

◆ SDF_3D_ACT

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::SDF_3D_ACT

0x00000190 Holds the value that controller is using for SDF_3D.

◆ RESERVED9

__IM uint32_t GFXSS_MIPIDSI_DWCMIPIDSI_Type::RESERVED9[923]