Description

Host Interface Registers (GFXSS_DC_DCNANO)

Data Fields
__IM uint32_t	GCREGDCCHIPREV

__IM uint32_t	GCREGDCCHIPDATE

__IM uint32_t	GCREGDCCHIPPATCHREV

__IM uint32_t	GCREGDCPRODUCTID

__IM uint32_t	RESERVED [5]

__IOM uint32_t	GCREGFRAMEBUFFERCONFIG

__IOM uint32_t	GCREGFRAMEBUFFERADDRESS

__IOM uint32_t	GCREGFRAMEBUFFERSTRIDE

__IM uint32_t	RESERVED1

__IOM uint32_t	GCREGDCTILEINCFG

__IOM uint32_t	GCREGDCTILEUVFRAMEBUFFERADR

__IOM uint32_t	GCREGDCTILEUVFRAMEBUFFERSTR

__IM uint32_t	RESERVED2 [6]

__IOM uint32_t	GCREGFRAMEBUFFERBACKGROUND

__IOM uint32_t	GCREGFRAMEBUFFERCOLORKEY

__IOM uint32_t	GCREGFRAMEBUFFERCOLORKEYHIGH

__IOM uint32_t	GCREGFRAMEBUFFERCLEARVALUE

__IOM uint32_t	GCREGVIDEOTL

__IOM uint32_t	GCREGFRAMEBUFFERSIZE

__IOM uint32_t	GCREGVIDEOGLOBALALPHA

__IOM uint32_t	GCREGBLENDSTACKORDER

__IOM uint32_t	GCREGVIDEOALPHABLENDCONFIG

__IOM uint32_t	GCREGOVERLAYCONFIG

__IOM uint32_t	GCREGOVERLAYADDRESS

__IOM uint32_t	GCREGOVERLAYSTRIDE

__IOM uint32_t	GCREGDCOVERLAYTILEINCFG

__IOM uint32_t	GCREGDCTILEUVOVERLAYADR

__IOM uint32_t	GCREGDCTILEUVOVERLAYSTR

__IOM uint32_t	GCREGOVERLAYTL

__IOM uint32_t	GCREGOVERLAYSIZE

__IOM uint32_t	GCREGOVERLAYCOLORKEY

__IOM uint32_t	GCREGOVERLAYCOLORKEYHIGH

__IOM uint32_t	GCREGOVERLAYALPHABLENDCONFIG

__IOM uint32_t	GCREGOVERLAYGLOBALALPHA

__IOM uint32_t	GCREGOVERLAYCLEARVALUE

__IOM uint32_t	GCREGOVERLAYCONFIG1

__IOM uint32_t	GCREGOVERLAYADDRESS1

__IOM uint32_t	GCREGOVERLAYSTRIDE1

__IOM uint32_t	GCREGOVERLAYTL1

__IOM uint32_t	GCREGOVERLAYSIZE1

__IOM uint32_t	GCREGOVERLAYCOLORKEY1

__IOM uint32_t	GCREGOVERLAYCOLORKEYHIGH1

__IOM uint32_t	GCREGOVERLAYALPHABLENDCONFIG1

__IOM uint32_t	GCREGOVERLAYGLOBALALPHA1

__IOM uint32_t	GCREGOVERLAYCLEARVALUE1

__IM uint32_t	RESERVED3 [2]

__IOM uint32_t	GCREGDISPLAYDITHERTABLELOW

__IOM uint32_t	GCREGDISPLAYDITHERTABLEHIGH

__IOM uint32_t	GCREGPANELCONFIG

__IOM uint32_t	GCREGPANELCONTROL

__IOM uint32_t	GCREGPANELFUNCTION

__OM uint32_t	GCREGPANELWORKING

__IM uint32_t	GCREGPANELSTATE

__IM uint32_t	RESERVED4

__IOM uint32_t	GCREGHDISPLAY

__IOM uint32_t	GCREGHSYNC

__IM uint32_t	RESERVED5 [2]

__IOM uint32_t	GCREGVDISPLAY

__IOM uint32_t	GCREGVSYNC

__IM uint32_t	GCREGDISPLAYCURRENTLOCATION

__OM uint32_t	GCREGGAMMAINDEX

__OM uint32_t	GCREGGAMMADATA

__IOM uint32_t	GCREGCURSORCONFIG

__IOM uint32_t	GCREGCURSORADDRESS

__IOM uint32_t	GCREGCURSORLOCATION

__IOM uint32_t	GCREGCURSORBACKGROUND

__IOM uint32_t	GCREGCURSORFOREGROUND

__IM uint32_t	GCREGDISPLAYINTR

__IOM uint32_t	GCREGDISPLAYINTRENABLE

__IOM uint32_t	GCREGDBICONFIG

__OM uint32_t	GCREGDBIIFRESET

__IOM uint32_t	GCREGDBIWRCHAR1

__IOM uint32_t	GCREGDBIWRCHAR2

__OM uint32_t	GCREGDBICMD

__IOM uint32_t	GCREGDPICONFIG

__IOM uint32_t	GCREGDBITYPECCFG

__IM uint32_t	GCREGDCSTATUS

__IOM uint32_t	GCREGSRCCONFIGENDIAN

__OM uint32_t	GCREGSOFTRESET

__IOM uint32_t	GCREGDCCONTROL

__IOM uint32_t	GCREGREGISTERTIMINGCONTROL

__IOM uint32_t	GCREGDEBUGCOUNTERSELECT

__IM uint32_t	GCREGDEBUGCOUNTERVALUE

__IM uint32_t	RESERVED6 [10]

__IOM uint32_t	GCREGLAYERCLOCKGATE

__IM uint32_t	GCREGDEBUGTOTVIDEOREQ

__IM uint32_t	GCREGDEBUGLSTVIDEOREQ

__IM uint32_t	GCREGDEBUGTOTVIDEORRB

__IM uint32_t	GCREGDEBUGLSTVIDEORRB

__IM uint32_t	GCREGDEBUGTOTOVERLAY0REQ

__IM uint32_t	GCREGDEBUGLSTOVERLAY0REQ

__IM uint32_t	GCREGDEBUGTOTOVERLAY0RRB

__IM uint32_t	GCREGDEBUGLSTOVERLAY0RRB

__IM uint32_t	GCREGDEBUGTOTOVERLAY1REQ

__IM uint32_t	GCREGDEBUGLSTOVERLAY1REQ

__IM uint32_t	GCREGDEBUGTOTOVERLAY1RRB

__IM uint32_t	GCREGDEBUGLSTOVERLAY1RRB

__IM uint32_t	GCREGDEBUGTOTCURSORREQ

__IM uint32_t	GCREGDEBUGLSTCURSORREQ

__IM uint32_t	GCREGDEBUGTOTCURSORRRB

__IM uint32_t	GCREGDEBUGLSTCURSORRRB

__IM uint32_t	GCREGDEBUGTOTDCREQ

__IM uint32_t	GCREGDEBUGLSTDCREQ

__IM uint32_t	GCREGDEBUGTOTDCRRB

__IM uint32_t	GCREGDEBUGLSTDCRRB

__IM uint32_t	GCREGDEBUGFRAMEANDMISFLAG

__IM uint32_t	RESERVED7 [2]

Field Documentation

◆ GCREGDCCHIPREV

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCCHIPREV

0x00000000 Chip Revision Register. Shows the revision for the chip in BCD. This register has no set reset value. It varies with the implementation. READ ONLY.

◆ GCREGDCCHIPDATE

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCCHIPDATE

0x00000004 Chip Date Register. Shows the release date for the IP in YYYYMMDD (year, month. day) format. This register has no set reset value. It varies with the implementation. READ ONLY.

◆ GCREGDCCHIPPATCHREV

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCCHIPPATCHREV

0x00000008 Patch Revision Register. Patch revision level for the chip. READ ONLY.

◆ GCREGDCPRODUCTID

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCPRODUCTID

0x0000000C Product Identification Register. READ ONLY.

◆ RESERVED

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED[5]

◆ GCREGFRAMEBUFFERCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERCONFIG

0x00000024 Frame Buffer Configuration Register. Frame Buffer and Timing control. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERADDRESS

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERADDRESS

0x00000028 Frame Buffer Base Address Register. Starting address of the frame buffer. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERSTRIDE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERSTRIDE

0x0000002C Frame Buffer Stride Register. Stride of the frame buffer in bytes. NOTE.. This register is double buffered.

◆ RESERVED1

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED1

◆ GCREGDCTILEINCFG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCTILEINCFG

0x00000034 Tile Input Configuration Register. Tile input configuration. NOTE.. This register is double buffered.

◆ GCREGDCTILEUVFRAMEBUFFERADR

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCTILEUVFRAMEBUFFERADR

0x00000038 Frame Buffer Tiled UV Base Address Register. UV frame buffer address when tile input. NOTE.. This register is double buffered.

◆ GCREGDCTILEUVFRAMEBUFFERSTR

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCTILEUVFRAMEBUFFERSTR

0x0000003C Frame Buffer Tiled UV Stride Register. UV frame buffer stride when tile input NOTE.. This register is double buffered.

◆ RESERVED2

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED2[6]

◆ GCREGFRAMEBUFFERBACKGROUND

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERBACKGROUND

0x00000058 Framebuffer background color. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERCOLORKEY

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERCOLORKEY

0x0000005C Framebuffer Color Key Start Address Register. Start of color key range of framebuffer. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERCOLORKEYHIGH

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERCOLORKEYHIGH

0x00000060 Framebuffer Color Key End Address Register. End of color key range of framebuffer. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERCLEARVALUE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERCLEARVALUE

0x00000064 Framebuffer Clear Value Register. Clear value used when dcregFrameBufferConfig.Clear is enabled, format is A8R8G8B8. NOTE.. This register is double buffered.

◆ GCREGVIDEOTL

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGVIDEOTL

0x00000068 Top left coordinate of panel pixel where the video should start. Be aware there is no panning inside the video. NOTE.. This register is double buffered.

◆ GCREGFRAMEBUFFERSIZE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGFRAMEBUFFERSIZE

0x0000006C video size information. NOTE.. This register is double buffered.

◆ GCREGVIDEOGLOBALALPHA

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGVIDEOGLOBALALPHA

0x00000070 Global alpha for the video. NOTE.. This register is double buffered.

◆ GCREGBLENDSTACKORDER

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGBLENDSTACKORDER

0x00000074 Set the video, overlay0, overlay1 order for blend. The 1st is the lowest layer, the 2nd is the middle layer, the 3rd is the highest layer. NOTE.. This register is double buffered.

◆ GCREGVIDEOALPHABLENDCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGVIDEOALPHABLENDCONFIG

0x00000078 Alpha Blending Configuration Register. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCONFIG

0x0000007C Overlay Configuration Register. Overlay control. NOTE.. This register is double buffered.

◆ GCREGOVERLAYADDRESS

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYADDRESS

0x00000080 Starting address of the overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYSTRIDE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYSTRIDE

0x00000084 Stride of the overlay in bytes. NOTE.. This register is double buffered.

◆ GCREGDCOVERLAYTILEINCFG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCOVERLAYTILEINCFG

0x00000088 Tile Input Configuration Register. Tile input configuration. NOTE.. This register is double buffered.

◆ GCREGDCTILEUVOVERLAYADR

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCTILEUVOVERLAYADR

0x0000008C Starting address of the overlay UV. NOTE.. This register is double buffered.

◆ GCREGDCTILEUVOVERLAYSTR

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCTILEUVOVERLAYSTR

0x00000090 Stride of the overlay UV in bytes. NOTE.. This register is double buffered.

◆ GCREGOVERLAYTL

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYTL

0x00000094 Top left coordinate of panel pixel where the overlay should start. Be aware there is no panning inside the overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYSIZE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYSIZE

0x00000098 overlay size information. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCOLORKEY

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCOLORKEY

0x0000009C Overlay Color Key Start Address Register. Start of color key range for overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCOLORKEYHIGH

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCOLORKEYHIGH

0x000000A0 Overlay Color Key End Address Register. End of color key range for overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYALPHABLENDCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYALPHABLENDCONFIG

0x000000A4 Alpha Blending Configuration Register. NOTE.. This register is double buffered.

◆ GCREGOVERLAYGLOBALALPHA

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYGLOBALALPHA

0x000000A8 Overlay global alpha value. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCLEARVALUE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCLEARVALUE

0x000000AC Overlay Clear Value Register. Clear value used when dcregOverlayConfig.Clear is enabled, Format is A8R8G8B8. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCONFIG1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCONFIG1

0x000000B0 Overlay Configuration Register. Overlay control. NOTE.. This register is double buffered.

◆ GCREGOVERLAYADDRESS1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYADDRESS1

0x000000B4 Starting address of the overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYSTRIDE1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYSTRIDE1

0x000000B8 Stride of the overlay in bytes. NOTE.. This register is double buffered.

◆ GCREGOVERLAYTL1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYTL1

0x000000BC Top left coordinate of panel pixel where the overlay should start. Be aware there is no panning inside the overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYSIZE1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYSIZE1

0x000000C0 overlay1 size information. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCOLORKEY1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCOLORKEY1

0x000000C4 Overlay Color Key Start Address Register. Start of color key range for overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCOLORKEYHIGH1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCOLORKEYHIGH1

0x000000C8 Overlay Color Key End Address Register. End of color key range for overlay. NOTE.. This register is double buffered.

◆ GCREGOVERLAYALPHABLENDCONFIG1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYALPHABLENDCONFIG1

0x000000CC Alpha Blending Configuration Register. NOTE.. This register is double buffered.

◆ GCREGOVERLAYGLOBALALPHA1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYGLOBALALPHA1

0x000000D0 Overlay global alpha value. NOTE.. This register is double buffered.

◆ GCREGOVERLAYCLEARVALUE1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGOVERLAYCLEARVALUE1

0x000000D4 Overlay Clear Value Register. Clear value used when dcregOverlayConfig.Clear is enabled, Format is A8R8G8B8. NOTE.. This register is double buffered.

◆ RESERVED3

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED3[2]

◆ GCREGDISPLAYDITHERTABLELOW

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDISPLAYDITHERTABLELOW

0x000000E0 Dither Threshold Table Register.

◆ GCREGDISPLAYDITHERTABLEHIGH

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDISPLAYDITHERTABLEHIGH

0x000000E4 Dither Threshold Table Register.

◆ GCREGPANELCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGPANELCONFIG

0x000000E8 Panel Configuration Register.

◆ GCREGPANELCONTROL

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGPANELCONTROL

0x000000EC Panel control Register.

◆ GCREGPANELFUNCTION

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGPANELFUNCTION

0x000000F0 Panel function Register. NOTE.. This register is double buffered.

◆ GCREGPANELWORKING

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGPANELWORKING

0x000000F4 Register to trigger Display Controller.

◆ GCREGPANELSTATE

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGPANELSTATE

0x000000F8 Register representing the Display Controller status. READ ONLY.

◆ RESERVED4

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED4

◆ GCREGHDISPLAY

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGHDISPLAY

0x00000100 Horizontal Display Total and Visible Pixel Count Register. Horizontal Total and Display End counters. NOTE.. This register is double buffered.

◆ GCREGHSYNC

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGHSYNC

0x00000104 Horizontal Sync Counter Register. Horizontal Sync counters. NOTE.. This register is double buffered.

◆ RESERVED5

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED5[2]

◆ GCREGVDISPLAY

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGVDISPLAY

0x00000110 Vertical Total and Visible Pixel Count Register. Vertical Total and Display End counters. NOTE.. This register is double buffered.

◆ GCREGVSYNC

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGVSYNC

0x00000114 Vertical Sync Counter Register. Vertical Sync counters. NOTE.. This register is double buffered.

◆ GCREGDISPLAYCURRENTLOCATION

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDISPLAYCURRENTLOCATION

0x00000118 Display Current Location Register. Current x,y location of display controller. READ ONLY.

◆ GCREGGAMMAINDEX

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGGAMMAINDEX

0x0000011C Gamma Index Register. Index into gamma table. See gcregGammaData for more information.

◆ GCREGGAMMADATA

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGGAMMADATA

0x00000120 Gamma Data Register. Translation values for the gamma table. When this register gets written, the data gets stored in the gamma table at the index specified by the gcregGammaIndex register. After the register is written, the index gets incremented.

◆ GCREGCURSORCONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGCURSORCONFIG

0x00000124 Cursor Configuration Register. Configuration register for the cursor. Double-buffered values in this register cannot be read while a flip is in progress. NOTE.. This register is double buffered.

◆ GCREGCURSORADDRESS

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGCURSORADDRESS

0x00000128 Cursor Base Address Register. Address of the cursor shape. NOTE.. This register is double buffered.

◆ GCREGCURSORLOCATION

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGCURSORLOCATION

0x0000012C Cursor Location Register. Location of the cursor on the owning display. NOTE.. This register is double buffered.

◆ GCREGCURSORBACKGROUND

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGCURSORBACKGROUND

0x00000130 Cursor Background Color Register. The background color for Masked cursors. NOTE.. This register is double buffered.

◆ GCREGCURSORFOREGROUND

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGCURSORFOREGROUND

0x00000134 Cursor Foreground Color Register. The foreground color for Masked cursors. NOTE.. This register is double buffered.

◆ GCREGDISPLAYINTR

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDISPLAYINTR

0x00000138 Display Interrupt Register. This is the interrupt register for the Display. This register will automatically clear after a read. The interrupt bit is set when the current frame buffer is used up. The interrupt signal will be pulled up only when the interrupt enable bit in register gcregDisplayIntrEnable is enabled. READ ONLY. When the access comes from a debugger (HMASTER[0] == 1), the clear by read function is disabled.

◆ GCREGDISPLAYINTRENABLE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDISPLAYINTRENABLE

0x0000013C Display Interrupt Enable Register. The interrupt enable register for display_0 (and display_1 if present). NOTE.. Interrupt enable for register gcregDisplayIntr. NOTE.. This register is double buffered.

◆ GCREGDBICONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBICONFIG

0x00000140 DBI Configuration Register. Configuration register for DBI output.

◆ GCREGDBIIFRESET

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBIIFRESET

0x00000144 DBI Reset Register. Reset DBI interface to idle state. WRITE ONLY.

◆ GCREGDBIWRCHAR1

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBIWRCHAR1

0x00000148 DBI Write AC Characteristics 1 Register. DBI write AC characteristics definition register 1

◆ GCREGDBIWRCHAR2

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBIWRCHAR2

0x0000014C DBI Write AC Characteristics 2 Register. DBI write AC characteristics definition register 2

◆ GCREGDBICMD

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBICMD

0x00000150 DBI Command Control Register. DBI Command in/out port. Writes to this register will send command/data to the DBI port. WRITE ONLY.

◆ GCREGDPICONFIG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDPICONFIG

0x00000154 DPI Configuration Register. The configuration register for DPI output. NOTE.. This register is double buffered.

◆ GCREGDBITYPECCFG

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDBITYPECCFG

0x00000158 DBI Type C Timing Control Register. DBI Type C write timing definition.

◆ GCREGDCSTATUS

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCSTATUS

0x0000015C Display Controller Status Register. READ ONLY.

◆ GCREGSRCCONFIGENDIAN

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGSRCCONFIGENDIAN

0x00000160 Endian control.

◆ GCREGSOFTRESET

__OM uint32_t GFXSS_DC_DCNANO_Type::GCREGSOFTRESET

0x00000164 Soft reset. WRITE ONLY.

◆ GCREGDCCONTROL

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDCCONTROL

0x00000168 Control register.

◆ GCREGREGISTERTIMINGCONTROL

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGREGISTERTIMINGCONTROL

0x0000016C Timing control register.

◆ GCREGDEBUGCOUNTERSELECT

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGCOUNTERSELECT

0x00000170 Debug Counter Select Register.

◆ GCREGDEBUGCOUNTERVALUE

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGCOUNTERVALUE

0x00000174 Debug Counter Value Register. Debug Counter Value as specified in gcregDebugCounterSelect. READ ONLY

◆ RESERVED6

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED6[10]

◆ GCREGLAYERCLOCKGATE

__IOM uint32_t GFXSS_DC_DCNANO_Type::GCREGLAYERCLOCKGATE

0x000001A0 Layer clock gater Register. disable video/overlay0/overlay1 clock gater

◆ GCREGDEBUGTOTVIDEOREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTVIDEOREQ

0x000001A4 debug registers.. count video current frame number of requested burst. READ ONLY

◆ GCREGDEBUGLSTVIDEOREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTVIDEOREQ

0x000001A8 debug registers.. count video last frame number of requested burst. READ ONLY

◆ GCREGDEBUGTOTVIDEORRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTVIDEORRB

0x000001AC debug registers.. count video current frame number of returned burst. READ ONLY

◆ GCREGDEBUGLSTVIDEORRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTVIDEORRB

0x000001B0 debug registers.. count video last frame number of returned burst. READ ONLY

◆ GCREGDEBUGTOTOVERLAY0REQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTOVERLAY0REQ

0x000001B4 debug registers.. count overlay0 current frame number of requested burst. READ ONLY

◆ GCREGDEBUGLSTOVERLAY0REQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTOVERLAY0REQ

0x000001B8 debug registers.. count overlay0 last frame number of requested burst. READ ONLY

◆ GCREGDEBUGTOTOVERLAY0RRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTOVERLAY0RRB

0x000001BC debug registers.. count overlay0 current frame number of returned burst. READ ONLY

◆ GCREGDEBUGLSTOVERLAY0RRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTOVERLAY0RRB

0x000001C0 debug registers.. count overlay0 last frame number of returned burst. READ ONLY

◆ GCREGDEBUGTOTOVERLAY1REQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTOVERLAY1REQ

0x000001C4 debug registers.. count overlay1 current frame number of requested burst. READ ONLY

◆ GCREGDEBUGLSTOVERLAY1REQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTOVERLAY1REQ

0x000001C8 debug registers.. count overlay1 last frame number of requested burst. READ ONLY

◆ GCREGDEBUGTOTOVERLAY1RRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTOVERLAY1RRB

0x000001CC debug registers.. count overlay1 current frame number of returned burst. READ ONLY

◆ GCREGDEBUGLSTOVERLAY1RRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTOVERLAY1RRB

0x000001D0 debug registers.. count overlay1 last frame number of returned burst. READ ONLY

◆ GCREGDEBUGTOTCURSORREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTCURSORREQ

0x000001D4 debug registers.. count cursor current frame number of requested burst. READ ONLY

◆ GCREGDEBUGLSTCURSORREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTCURSORREQ

0x000001D8 debug registers.. count cursor last frame number of requested burst. READ ONLY

◆ GCREGDEBUGTOTCURSORRRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTCURSORRRB

0x000001DC debug registers.. count cursor current frame number of returned burst. READ ONLY

◆ GCREGDEBUGLSTCURSORRRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTCURSORRRB

0x000001E0 debug registers.. count cursor last frame number of returned burst. READ ONLY

◆ GCREGDEBUGTOTDCREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTDCREQ

0x000001E4 debug registers.. count DC current frame number of requested burst. READ ONLY

◆ GCREGDEBUGLSTDCREQ

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTDCREQ

0x000001E8 debug registers.. count DC last frame number of requested burst. READ ONLY

◆ GCREGDEBUGTOTDCRRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGTOTDCRRB

0x000001EC debug registers.. count DC current frame number of returned burst. READ ONLY

◆ GCREGDEBUGLSTDCRRB

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGLSTDCRRB

0x000001F0 debug registers.. count DC last frame number of returned burst. READ ONLY

◆ GCREGDEBUGFRAMEANDMISFLAG

__IM uint32_t GFXSS_DC_DCNANO_Type::GCREGDEBUGFRAMEANDMISFLAG

0x000001F4 debug registers. READ ONLY

◆ RESERVED7

__IM uint32_t GFXSS_DC_DCNANO_Type::RESERVED7[2]