Description

Cryptography component (CRYPTO_V2)

Data Fields
__IOM uint32_t	CTL

__IM uint32_t	RESERVED

__IOM uint32_t	RAM_PWR_CTL

__IOM uint32_t	RAM_PWR_DELAY_CTL

__IOM uint32_t	ECC_CTL

__IM uint32_t	RESERVED1 [3]

__IM uint32_t	ERROR_STATUS0

__IOM uint32_t	ERROR_STATUS1

__IM uint32_t	RESERVED2 [54]

__IOM uint32_t	INTR

__IOM uint32_t	INTR_SET

__IOM uint32_t	INTR_MASK

__IM uint32_t	INTR_MASKED

__IM uint32_t	RESERVED3 [60]

__IOM uint32_t	PR_LFSR_CTL0

__IOM uint32_t	PR_LFSR_CTL1

__IOM uint32_t	PR_LFSR_CTL2

__IOM uint32_t	PR_MAX_CTL

__IOM uint32_t	PR_CMD

__IM uint32_t	RESERVED4

__IOM uint32_t	PR_RESULT

__IM uint32_t	RESERVED5 [25]

__IOM uint32_t	TR_CTL0

__IOM uint32_t	TR_CTL1

__IOM uint32_t	TR_CTL2

__IM uint32_t	TR_STATUS

__IOM uint32_t	TR_CMD

__IM uint32_t	RESERVED6

__IOM uint32_t	TR_RESULT

__IM uint32_t	RESERVED7

__IOM uint32_t	TR_GARO_CTL

__IOM uint32_t	TR_FIRO_CTL

__IM uint32_t	RESERVED8 [6]

__IOM uint32_t	TR_MON_CTL

__IM uint32_t	RESERVED9

__IOM uint32_t	TR_MON_CMD

__IM uint32_t	RESERVED10

__IOM uint32_t	TR_MON_RC_CTL

__IM uint32_t	RESERVED11

__IM uint32_t	TR_MON_RC_STATUS0

__IM uint32_t	TR_MON_RC_STATUS1

__IOM uint32_t	TR_MON_AP_CTL

__IM uint32_t	RESERVED12

__IM uint32_t	TR_MON_AP_STATUS0

__IM uint32_t	TR_MON_AP_STATUS1

__IM uint32_t	RESERVED13 [837]

__IM uint32_t	STATUS

__IM uint32_t	RESERVED14 [14]

__IOM uint32_t	INSTR_FF_CTL

__IM uint32_t	INSTR_FF_STATUS

__OM uint32_t	INSTR_FF_WR

__IM uint32_t	RESERVED15 [29]

__IM uint32_t	LOAD0_FF_STATUS

__IM uint32_t	RESERVED16 [3]

__IM uint32_t	LOAD1_FF_STATUS

__IM uint32_t	RESERVED17 [7]

__IM uint32_t	STORE_FF_STATUS

__IM uint32_t	RESERVED18 [3]

__IOM uint32_t	AES_CTL

__IM uint32_t	RESERVED19 [31]

__IOM uint32_t	RESULT

__IM uint32_t	RESERVED20 [159]

__IOM uint32_t	CRC_CTL

__IM uint32_t	RESERVED21 [3]

__IOM uint32_t	CRC_DATA_CTL

__IM uint32_t	RESERVED22 [3]

__IOM uint32_t	CRC_POL_CTL

__IM uint32_t	RESERVED23 [7]

__IOM uint32_t	CRC_REM_CTL

__IM uint32_t	RESERVED24

__IM uint32_t	CRC_REM_RESULT

__IM uint32_t	RESERVED25 [13]

__IOM uint32_t	VU_CTL0

__IOM uint32_t	VU_CTL1

__IOM uint32_t	VU_CTL2

__IM uint32_t	RESERVED26

__IM uint32_t	VU_STATUS

__IM uint32_t	RESERVED27 [11]

__IM uint32_t	VU_RF_DATA [16]

__IM uint32_t	RESERVED28 [704]

__IOM uint32_t	DEV_KEY_ADDR0_CTL

__IOM uint32_t	DEV_KEY_ADDR0

__IM uint32_t	RESERVED29 [6]

__IOM uint32_t	DEV_KEY_ADDR1_CTL

__IOM uint32_t	DEV_KEY_ADDR1

__IM uint32_t	RESERVED30 [22]

__IM uint32_t	DEV_KEY_STATUS

__IM uint32_t	RESERVED31 [31]

__IOM uint32_t	DEV_KEY_CTL0

__IM uint32_t	RESERVED32 [7]

__IOM uint32_t	DEV_KEY_CTL1

__IM uint32_t	RESERVED33 [6071]

__IOM uint32_t	MEM_BUFF [8192]

Field Documentation

◆ CTL

__IOM uint32_t CRYPTO_V2_Type::CTL

0x00000000 Control

◆ RESERVED

__IM uint32_t CRYPTO_V2_Type::RESERVED

◆ RAM_PWR_CTL

__IOM uint32_t CRYPTO_V2_Type::RAM_PWR_CTL

0x00000008 SRAM power control

◆ RAM_PWR_DELAY_CTL

__IOM uint32_t CRYPTO_V2_Type::RAM_PWR_DELAY_CTL

0x0000000C SRAM power delay control

◆ ECC_CTL

__IOM uint32_t CRYPTO_V2_Type::ECC_CTL

0x00000010 ECC control

◆ RESERVED1

__IM uint32_t CRYPTO_V2_Type::RESERVED1[3]

◆ ERROR_STATUS0

__IM uint32_t CRYPTO_V2_Type::ERROR_STATUS0

0x00000020 Error status 0

◆ ERROR_STATUS1

__IOM uint32_t CRYPTO_V2_Type::ERROR_STATUS1

0x00000024 Error status 1

◆ RESERVED2

__IM uint32_t CRYPTO_V2_Type::RESERVED2[54]

◆ INTR

__IOM uint32_t CRYPTO_V2_Type::INTR

0x00000100 Interrupt register

◆ INTR_SET

__IOM uint32_t CRYPTO_V2_Type::INTR_SET

0x00000104 Interrupt set register

◆ INTR_MASK

__IOM uint32_t CRYPTO_V2_Type::INTR_MASK

0x00000108 Interrupt mask register

◆ INTR_MASKED

__IM uint32_t CRYPTO_V2_Type::INTR_MASKED

0x0000010C Interrupt masked register

◆ RESERVED3

__IM uint32_t CRYPTO_V2_Type::RESERVED3[60]

◆ PR_LFSR_CTL0

__IOM uint32_t CRYPTO_V2_Type::PR_LFSR_CTL0

0x00000200 Pseudo random LFSR control 0

◆ PR_LFSR_CTL1

__IOM uint32_t CRYPTO_V2_Type::PR_LFSR_CTL1

0x00000204 Pseudo random LFSR control 1

◆ PR_LFSR_CTL2

__IOM uint32_t CRYPTO_V2_Type::PR_LFSR_CTL2

0x00000208 Pseudo random LFSR control 2

◆ PR_MAX_CTL

__IOM uint32_t CRYPTO_V2_Type::PR_MAX_CTL

0x0000020C Pseudo random maximum control

◆ PR_CMD

__IOM uint32_t CRYPTO_V2_Type::PR_CMD

0x00000210 Pseudo random command

◆ RESERVED4

__IM uint32_t CRYPTO_V2_Type::RESERVED4

◆ PR_RESULT

__IOM uint32_t CRYPTO_V2_Type::PR_RESULT

0x00000218 Pseudo random result

◆ RESERVED5

__IM uint32_t CRYPTO_V2_Type::RESERVED5[25]

◆ TR_CTL0

__IOM uint32_t CRYPTO_V2_Type::TR_CTL0

0x00000280 True random control 0

◆ TR_CTL1

__IOM uint32_t CRYPTO_V2_Type::TR_CTL1

0x00000284 True random control 1

◆ TR_CTL2

__IOM uint32_t CRYPTO_V2_Type::TR_CTL2

0x00000288 True random control 2

◆ TR_STATUS

__IM uint32_t CRYPTO_V2_Type::TR_STATUS

0x0000028C True random status

◆ TR_CMD

__IOM uint32_t CRYPTO_V2_Type::TR_CMD

0x00000290 True random command

◆ RESERVED6

__IM uint32_t CRYPTO_V2_Type::RESERVED6

◆ TR_RESULT

__IOM uint32_t CRYPTO_V2_Type::TR_RESULT

0x00000298 True random result

◆ RESERVED7

__IM uint32_t CRYPTO_V2_Type::RESERVED7

◆ TR_GARO_CTL

__IOM uint32_t CRYPTO_V2_Type::TR_GARO_CTL

0x000002A0 True random GARO control

◆ TR_FIRO_CTL

__IOM uint32_t CRYPTO_V2_Type::TR_FIRO_CTL

0x000002A4 True random FIRO control

◆ RESERVED8

__IM uint32_t CRYPTO_V2_Type::RESERVED8[6]

◆ TR_MON_CTL

__IOM uint32_t CRYPTO_V2_Type::TR_MON_CTL

0x000002C0 True random monitor control

◆ RESERVED9

__IM uint32_t CRYPTO_V2_Type::RESERVED9

◆ TR_MON_CMD

__IOM uint32_t CRYPTO_V2_Type::TR_MON_CMD

0x000002C8 True random monitor command

◆ RESERVED10

__IM uint32_t CRYPTO_V2_Type::RESERVED10

◆ TR_MON_RC_CTL

__IOM uint32_t CRYPTO_V2_Type::TR_MON_RC_CTL

0x000002D0 True random monitor RC control

◆ RESERVED11

__IM uint32_t CRYPTO_V2_Type::RESERVED11

◆ TR_MON_RC_STATUS0

__IM uint32_t CRYPTO_V2_Type::TR_MON_RC_STATUS0

0x000002D8 True random monitor RC status 0

◆ TR_MON_RC_STATUS1

__IM uint32_t CRYPTO_V2_Type::TR_MON_RC_STATUS1

0x000002DC True random monitor RC status 1

◆ TR_MON_AP_CTL

__IOM uint32_t CRYPTO_V2_Type::TR_MON_AP_CTL

0x000002E0 True random monitor AP control

◆ RESERVED12

__IM uint32_t CRYPTO_V2_Type::RESERVED12

◆ TR_MON_AP_STATUS0

__IM uint32_t CRYPTO_V2_Type::TR_MON_AP_STATUS0

0x000002E8 True random monitor AP status 0

◆ TR_MON_AP_STATUS1

__IM uint32_t CRYPTO_V2_Type::TR_MON_AP_STATUS1

0x000002EC True random monitor AP status 1

◆ RESERVED13

__IM uint32_t CRYPTO_V2_Type::RESERVED13[837]

◆ STATUS

__IM uint32_t CRYPTO_V2_Type::STATUS

0x00001004 Status

◆ RESERVED14

__IM uint32_t CRYPTO_V2_Type::RESERVED14[14]

◆ INSTR_FF_CTL

__IOM uint32_t CRYPTO_V2_Type::INSTR_FF_CTL

0x00001040 Instruction FIFO control

◆ INSTR_FF_STATUS

__IM uint32_t CRYPTO_V2_Type::INSTR_FF_STATUS

0x00001044 Instruction FIFO status

◆ INSTR_FF_WR

__OM uint32_t CRYPTO_V2_Type::INSTR_FF_WR

0x00001048 Instruction FIFO write

◆ RESERVED15

__IM uint32_t CRYPTO_V2_Type::RESERVED15[29]

◆ LOAD0_FF_STATUS

__IM uint32_t CRYPTO_V2_Type::LOAD0_FF_STATUS

0x000010C0 Load 0 FIFO status

◆ RESERVED16

__IM uint32_t CRYPTO_V2_Type::RESERVED16[3]

◆ LOAD1_FF_STATUS

__IM uint32_t CRYPTO_V2_Type::LOAD1_FF_STATUS

0x000010D0 Load 1 FIFO status

◆ RESERVED17

__IM uint32_t CRYPTO_V2_Type::RESERVED17[7]

◆ STORE_FF_STATUS

__IM uint32_t CRYPTO_V2_Type::STORE_FF_STATUS

0x000010F0 Store FIFO status

◆ RESERVED18

__IM uint32_t CRYPTO_V2_Type::RESERVED18[3]

◆ AES_CTL

__IOM uint32_t CRYPTO_V2_Type::AES_CTL

0x00001100 AES control

◆ RESERVED19

__IM uint32_t CRYPTO_V2_Type::RESERVED19[31]

◆ RESULT

__IOM uint32_t CRYPTO_V2_Type::RESULT

0x00001180 Result

◆ RESERVED20

__IM uint32_t CRYPTO_V2_Type::RESERVED20[159]

◆ CRC_CTL

__IOM uint32_t CRYPTO_V2_Type::CRC_CTL

0x00001400 CRC control

◆ RESERVED21

__IM uint32_t CRYPTO_V2_Type::RESERVED21[3]

◆ CRC_DATA_CTL

__IOM uint32_t CRYPTO_V2_Type::CRC_DATA_CTL

0x00001410 CRC data control

◆ RESERVED22

__IM uint32_t CRYPTO_V2_Type::RESERVED22[3]

◆ CRC_POL_CTL

__IOM uint32_t CRYPTO_V2_Type::CRC_POL_CTL

0x00001420 CRC polynomial control

◆ RESERVED23

__IM uint32_t CRYPTO_V2_Type::RESERVED23[7]

◆ CRC_REM_CTL

__IOM uint32_t CRYPTO_V2_Type::CRC_REM_CTL

0x00001440 CRC remainder control

◆ RESERVED24

__IM uint32_t CRYPTO_V2_Type::RESERVED24

◆ CRC_REM_RESULT

__IM uint32_t CRYPTO_V2_Type::CRC_REM_RESULT

0x00001448 CRC remainder result

◆ RESERVED25

__IM uint32_t CRYPTO_V2_Type::RESERVED25[13]

◆ VU_CTL0

__IOM uint32_t CRYPTO_V2_Type::VU_CTL0

0x00001480 Vector unit control 0

◆ VU_CTL1

__IOM uint32_t CRYPTO_V2_Type::VU_CTL1

0x00001484 Vector unit control 1

◆ VU_CTL2

__IOM uint32_t CRYPTO_V2_Type::VU_CTL2

0x00001488 Vector unit control 2

◆ RESERVED26

__IM uint32_t CRYPTO_V2_Type::RESERVED26

◆ VU_STATUS

__IM uint32_t CRYPTO_V2_Type::VU_STATUS

0x00001490 Vector unit status

◆ RESERVED27

__IM uint32_t CRYPTO_V2_Type::RESERVED27[11]

◆ VU_RF_DATA

__IM uint32_t CRYPTO_V2_Type::VU_RF_DATA[16]

0x000014C0 Vector unit register-file

◆ RESERVED28

__IM uint32_t CRYPTO_V2_Type::RESERVED28[704]

◆ DEV_KEY_ADDR0_CTL

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_ADDR0_CTL

0x00002000 Device key address 0 control

◆ DEV_KEY_ADDR0

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_ADDR0

0x00002004 Device key address 0

◆ RESERVED29

__IM uint32_t CRYPTO_V2_Type::RESERVED29[6]

◆ DEV_KEY_ADDR1_CTL

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_ADDR1_CTL

0x00002020 Device key address 1 control

◆ DEV_KEY_ADDR1

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_ADDR1

0x00002024 Device key address 1 control

◆ RESERVED30

__IM uint32_t CRYPTO_V2_Type::RESERVED30[22]

◆ DEV_KEY_STATUS

__IM uint32_t CRYPTO_V2_Type::DEV_KEY_STATUS

0x00002080 Device key status

◆ RESERVED31

__IM uint32_t CRYPTO_V2_Type::RESERVED31[31]

◆ DEV_KEY_CTL0

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_CTL0

0x00002100 Device key control 0

◆ RESERVED32

__IM uint32_t CRYPTO_V2_Type::RESERVED32[7]

◆ DEV_KEY_CTL1

__IOM uint32_t CRYPTO_V2_Type::DEV_KEY_CTL1

0x00002120 Device key control 1

◆ RESERVED33

__IM uint32_t CRYPTO_V2_Type::RESERVED33[6071]

◆ MEM_BUFF

__IOM uint32_t CRYPTO_V2_Type::MEM_BUFF[8192]

0x00008000 Memory buffer