Reset cause

General Description

Define RESET_CAUSE mask values.

Macros
#define	CY_SYSLIB_RESET_HWWDT   (0x0001U)
	A basic WatchDog Timer (WDT) reset has occurred since the last power cycle.
#define	CY_SYSLIB_RESET_ACT_FAULT   (0x0002U)
	The fault logging system requested a reset from its Active logic.
#define	CY_SYSLIB_RESET_DPSLP_FAULT   (0x0004U)
	The fault logging system requested a reset from its Deep-Sleep logic.
#define	CY_SYSLIB_RESET_TC_DBGRESET   (0x0008U)
	The fault logging system requested a reset from its Test Controller or debugger asserted test. More...
#define	CY_SYSLIB_RESET_SOFT0   (0x0010U)
	SYSCPUSS (M33 core) requested a system reset through its SYSRESETREQ. More...
#define	CY_SYSLIB_RESET_SOFT   CY_SYSLIB_RESET_SOFT0
	Backwards compatibility alias for CY_SYSLIB_RESET_SOFT0.
#define	CY_SYSLIB_RESET_SOFT1   (0x0020U)
	APPCPUSS (M55 core) requested a system reset through its SYSRESETREQ. More...
#define	CY_SYSLIB_RESET_SOFT2   (0x0040U)
	M0SECCPUSS (M0SEC core) requested a system reset through its SYSRESETREQ. More...
#define	CY_SYSLIB_RESET_SWWDT0   (0x0100U)
	The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle.
#define	CY_SYSLIB_RESET_SWWDT1   (0x0200U)
	The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle.
#define	CY_SYSLIB_RESET_SWWDT2   (0x0400U)
	The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle.
#define	CY_SYSLIB_RESET_SWWDT3   (0x0800U)
	The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle.
#define	CY_SYSLIB_RESET_DS_OFF_WAKEUP   (0x02000U)
	The reset has occurred on a wakeup from DS OFF power mode.
#define	CY_SYSLIB_RESET_XRES   (0x04000U)
	External XRES pin was asserted. More...
#define	CY_SYSLIB_RESET_BODVDDD   (0x08000U)
	External VDDD supply crossed brown-out limit. More...
#define	CY_SYSLIB_RESET_CSV_LOSS_WAKEUP   (0x10000U)
	The reset has occurred on a loss of high-frequency clock.
#define	CY_SYSLIB_RESET_CSV_ERROR_WAKEUP   (0x20000U)
	The reset has occurred due to frequency error of high-frequency clock.
#define	CY_SYSLIB_RESET_BODVCCD   (0x80000U)
	Internal VCCD core supply crossed the brown-out limit. More...
#define	CY_SYSLIB_RESET_BODVBAT   (0x100000U)
	External VBAT supply crossed brown-out limit. More...
#define	CY_SYSLIB_RESET_OVDVCCD   (0x400000U)
	Overvoltage detection on the internal core VCCD supply. More...
#define	CY_SYSLIB_RESET_PXRES   (0x10000000U)
	PXRES triggered. More...
#define	CY_SYSLIB_RESET_STRUCT_XRES   (0x20000000U)
	Structural reset was asserted. More...
#define	CY_SYSLIB_RESET_PORVDDD   (0x40000000U)
	Indicator that a POR occurred. More...
#define	CY_SYSLIB_RESET_HIB_WAKEUP   (0x80000000U)
	The reset has occurred on a wakeup from Hibernate power mode.
#define	CY_SYSLIB_HIBERNATE_TOKEN   (0x1BU)
	Token to detect the reset has occurred on a wakeup from Hibernate power mode.
#define	CY_SYSLIB_DEEP_SLEEP_OFF_TOKEN   (0x3BU)
	Token to detect the reset has occurred on a wakeup from DS OFF power mode.

Macro Definition Documentation

CY_SYSLIB_RESET_TC_DBGRESET

#define CY_SYSLIB_RESET_TC_DBGRESET   (0x0008U)

The fault logging system requested a reset from its Test Controller or debugger asserted test.

Note

This macro is available for devices having M33SYSCPUSS IP.

CY_SYSLIB_RESET_SOFT0

#define CY_SYSLIB_RESET_SOFT0   (0x0010U)

SYSCPUSS (M33 core) requested a system reset through its SYSRESETREQ.

This can be done via a debugger probe or in firmware.

CY_SYSLIB_RESET_SOFT1

#define CY_SYSLIB_RESET_SOFT1   (0x0020U)

APPCPUSS (M55 core) requested a system reset through its SYSRESETREQ.

This can be done via a debugger probe or in firmware.

CY_SYSLIB_RESET_SOFT2

#define CY_SYSLIB_RESET_SOFT2   (0x0040U)

M0SECCPUSS (M0SEC core) requested a system reset through its SYSRESETREQ.

This can be done via a debugger probe or in firmware.

CY_SYSLIB_RESET_XRES

#define CY_SYSLIB_RESET_XRES   (0x04000U)

External XRES pin was asserted.

This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD or WDT.

CY_SYSLIB_RESET_BODVDDD

#define CY_SYSLIB_RESET_BODVDDD   (0x08000U)

External VDDD supply crossed brown-out limit.

Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit.

CY_SYSLIB_RESET_BODVCCD

#define CY_SYSLIB_RESET_BODVCCD   (0x80000U)

Internal VCCD core supply crossed the brown-out limit.

Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions.

CY_SYSLIB_RESET_BODVBAT

#define CY_SYSLIB_RESET_BODVBAT   (0x100000U)

External VBAT supply crossed brown-out limit.

Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit.

CY_SYSLIB_RESET_OVDVCCD

#define CY_SYSLIB_RESET_OVDVCCD   (0x400000U)

Overvoltage detection on the internal core VCCD supply.

This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD *XRES, or WDT.

CY_SYSLIB_RESET_PXRES

#define CY_SYSLIB_RESET_PXRES   (0x10000000U)

PXRES triggered.

This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD, *XRES, or WDT. Hardware clears this bit during POR.

CY_SYSLIB_RESET_STRUCT_XRES

#define CY_SYSLIB_RESET_STRUCT_XRES   (0x20000000U)

Structural reset was asserted.

This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD, *XRES, or WDT. Hardware clears this bit during POR.

CY_SYSLIB_RESET_PORVDDD

#define CY_SYSLIB_RESET_PORVDDD   (0x40000000U)

Indicator that a POR occurred.

This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes.