Data Structures

General Description

Data Structures
struct	cy_stc_scb_i2c_config_t
	I2C configuration structure. More...
struct	cy_stc_scb_i2c_context_t
	I2C context structure. More...
struct	cy_stc_scb_i2c_master_xfer_config_t
	The I2C Master transfer structure. More...

Typedefs
typedef void(*	cy_cb_scb_i2c_handle_events_t) (uint32_t event)
	Provides the typedef for the callback function called in the Cy_SCB_I2C_Interrupt to notify the user about occurrences of I2C Callback Events.
typedef cy_en_scb_i2c_command_t(*	cy_cb_scb_i2c_handle_addr_t) (uint32_t event)
	Provides the typedef for the callback function called in the Cy_SCB_I2C_Interrupt to notify the user about occurrences of I2C Address Callback Events. More...

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Data Structure Documentation

cy_stc_scb_i2c_config_t

struct cy_stc_scb_i2c_config_t

Data Fields
cy_en_scb_i2c_mode_t	i2cMode	Specifies the mode of operation.
bool	useRxFifo	The SCB provides an RX FIFO in hardware (consult the selected device datasheet to get the actual FIFO size). The useRxFifo field defines how the driver firmware reads data from the RX FIFO: If this option is enabled, the hardware is configured to automatically ACK incoming data, and interrupt is enabled to take data out of the RX FIFO when it has some number of bytes (typically, when it is half full). If this option is disabled, the interrupt is enabled to take data out of the RX FIFO when a byte is available. Also, hardware does not automatically ACK the data. Firmware must tell the hardware to ACK the byte (so each byte requires interrupt processing). Typically, this option should be enabled to configure hardware to automatically ACK incoming data. Otherwise hardware might not get the command to ACK or NACK a byte fast enough, and clock stretching is applied (the transaction is delayed) until the command is set. When this option is enabled, the number of interrupts required to process the transaction is significantly reduced because several bytes are handled at once. However, there is a side effect: For master mode, the drawback is that the master may receive more data than desired due to the interrupt latency. An interrupt fires when the second-to-last byte has been received. This interrupt tells the hardware to stop receiving data. If the latency of this interrupt is longer than one transaction of the byte on the I2C bus, then the hardware automatically ACKs the following bytes until the interrupt is serviced or the RX FIFO becomes full. For slave mode, the drawback is that the slave only NACKs the master when the RX FIFO becomes full, NOT when the slave write firmware buffer becomes full. In either master or slave mode, all received extra bytes are dropped. Note The useRxFifo option is not available if acceptAddrInFifo is true.
bool	useTxFifo	The SCB provides a TX FIFO in hardware (consult the selected device datasheet to get the actual FIFO size). The useTxFifo option defines how the driver firmware loads data into the TX FIFO: If this option is enabled, the TX FIFO is fully loaded with data and the interrupt is enabled to keep the TX FIFO loaded until the end of the transaction. If this option is disabled, a single byte is loaded into the TX FIFO and the interrupt enabled to load the next byte when the TX FIFO becomes empty (so each byte requires interrupt processing). Typically, this option should be enabled to keep the TX FIFO loaded with data and reduce the probability of clock stretching. When there is no data to transfer, clock stretching is applied (the transaction is delayed) until the data is loaded. When this option is enabled, the number of interrupts required to process the transaction is significantly reduced because several bytes are handled at once. The drawback of enabling useTxFifo is that the abort operation clears the TX FIFO. The TX FIFO clear operation also clears the shift register. As a result the shifter may be cleared in the middle of a byte transaction, corrupting it. The remaining bits to transaction within the corrupted byte are complemented with 1s. If this is an issue, then do not enable this option.
uint8_t	slaveAddress	The 7-bit right justified slave address, used only for the slave mode.
uint8_t	slaveAddressMask	The slave address mask is used to mask bits of the slave address during the address match procedure (it is used only for the slave mode). Bit 0 of the address mask corresponds to the read/write direction bit and is always a do not care in the address match therefore must be set 0. Bit value 0 - excludes bit from address comparison. Bit value 1 - the bit needs to match with the corresponding bit of the I2C slave address.
bool	acceptAddrInFifo	True - the slave address is accepted in the RX FIFO, false - the slave addresses are not accepted in the RX FIFO.
bool	ackGeneralAddr	True - accept the general call address; false - ignore the general call address.
bool	enableWakeFromSleep	When set, the slave will wake the device from Deep Sleep on an address match (the device datasheet must be consulted to determine which SCBs support this mode)
bool	enableDigitalFilter	Enables a digital 3-tap median filter to be applied to the inputs of filter glitches on the lines.
uint32_t	lowPhaseDutyCycle	The number of SCB clock cycles in the low phase of SCL. Only applicable in master modes. The valid range is 7 to 16.
uint32_t	highPhaseDutyCycle	The number of SCB clock cycles in the high phase of SCL. Only applicable in master modes. The valid range is 5 to 16. Please refer to the section group_scb_i2c_mclk_sync for more information.

cy_stc_scb_i2c_context_t

struct cy_stc_scb_i2c_context_t

cy_stc_scb_i2c_master_xfer_config_t

struct cy_stc_scb_i2c_master_xfer_config_t

Data Fields
uint8_t	slaveAddress	The 7-bit right justified slave address to communicate with.
uint8_t *	buffer	The pointer to the buffer for data to read from the slave or data to write into the slave.
uint32_t	bufferSize	The size of the buffer.
bool	xferPending	The transfer operation is pending - the stop condition will not be generated. A new transfer starts from start condition and ends with or without stop condition. The stop condition releases I2C bus from master control. When stop is not generated master keeps bus control (transfer is pending) and can issue the next transfer using restart condition instead of start. The I2C driver automatically generates start or restart condition depends on current state. Note if master lost arbitration during transfer it stops control the bus and does not send/receive data or generate stop condition - the transfer ends.

Typedef Documentation

cy_cb_scb_i2c_handle_addr_t

typedef cy_en_scb_i2c_command_t(* cy_cb_scb_i2c_handle_addr_t) (uint32_t event)

Provides the typedef for the callback function called in the Cy_SCB_I2C_Interrupt to notify the user about occurrences of I2C Address Callback Events.

This callback must return a decision to ACK (continue transaction) or NAK (end transaction) the received address. Note if the slave is configured to accept an address in RX FIFO, it must read from it using the Cy_SCB_ReadRxFifo function.