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#define | CY_I3C_INTR_TX_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_TX_THLD_STS_Msk |
| | The number of empty locations in the transmit buffer is greater than or equal to the specified threshold value.
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#define | CY_I3C_INTR_RX_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_RX_THLD_STS_Msk |
| | The number of elements in the receive buffer is greater than or equal to the specified threshold value.
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#define | CY_I3C_INTR_IBI_BUFFER_THLD_STS I3C_CORE_INTR_STATUS_IBI_THLD_STS_Msk |
| | The number of elements in the IBI buffer is greater than or equal to the specified threshold value.
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#define | CY_I3C_INTR_CMD_QUEUE_READY_STS I3C_CORE_INTR_STATUS_CMD_QUEUE_READY_STS_Msk |
| | The number of empty locations in the command queue is greater than or equal to the specified threshold value.
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#define | CY_I3C_INTR_RESP_READY_STS I3C_CORE_INTR_STATUS_RESP_READY_STS_Msk |
| | The number of elements in the response queue is greater than or equal to the specified threshold value.
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#define | CY_I3C_INTR_TRANSFER_ABORT_STS I3C_CORE_INTR_STATUS_TRANSFER_ABORT_STS_Msk |
| | The transfer is aborted.
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#define | CY_I3C_INTR_CCC_UPDATED_STS I3C_CORE_INTR_STATUS_CCC_UPDATED_STS_Msk |
| | The CCC registers are updated by the I3C Controller through CCC commands.
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#define | CY_I3C_INTR_DYN_ADDR_ASSGN_STS I3C_CORE_INTR_STATUS_DYN_ADDR_ASSGN_STS_Msk |
| | The dynamic address of the device is assigned through SETDASA or ENTDAA CCC.
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#define | CY_I3C_INTR_TRANSFER_ERR_STS I3C_CORE_INTR_STATUS_TRANSFER_ERR_STS_Msk |
| | Error occurred in the transfer.
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#define | CY_I3C_INTR_DEFTGT_STS I3C_CORE_INTR_STATUS_DEFTGT_STS_Msk |
| | DEFTGT CCC is received.
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#define | CY_I3C_INTR_READ_REQ_RECV_STS I3C_CORE_INTR_STATUS_READ_REQ_RECV_STS_Msk |
| | The read request is received from the current controller; command queue is empty.
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#define | CY_I3C_INTR_IBI_UPDATED_STS I3C_CORE_INTR_STATUS_IBI_UPDATED_STS_Msk |
| | The IBI request initiated via TIR request register is addressed and status is updated.
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#define | CY_I3C_INTR_BUSOWNER_UPDATED_STS I3C_CORE_INTR_STATUS_BUSOWNER_UPDATED_STS_Msk |
| | The role of the controller is changed.
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#define | CY_I3C_INTR_TGT_RST_PATTERN_DET_STS I3C_CORE_INTR_STATUS_TGT_RST_PATTERN_DET_STS_Msk |
| | Target reset pattern detected.
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| #define | CY_I3C_TGT_INTR_Msk |
| | Provides the list of allowed sources for target mode. More...
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