PSOC E8XXGP Device Support Library

General Description

Data Structures

struct  cy_stc_gpio_prt_config_t
 This structure is used to initialize a port of GPIO pins. More...
 
struct  cy_stc_gpio_pin_config_t
 This structure is used to initialize a single GPIO pin. More...
 

Data Structure Documentation

◆ cy_stc_gpio_prt_config_t

struct cy_stc_gpio_prt_config_t
Data Fields
uint32_t out Initial output data for the IO pins in the port.
uint32_t intrMask Interrupt enable mask for the port interrupt.
uint32_t intrCfg Port pin interrupt edge detection configuration.
uint32_t cfg Port pin drive modes and input buffer enable configuration.
uint32_t cfgIn Port pin input buffer configuration.
uint32_t cfgOut Port pin output buffer configuration.
uint32_t cfgSIO Port SIO pins configuration.
uint32_t sel0Active HSIOM selection for port pins 0,1,2,3.
uint32_t sel1Active HSIOM selection for port pins 4,5,6,7.
uint32_t cfgSlew Port slew rate configuration.
uint32_t cfgDriveSel0 Drive strength configuration for pins 0,1,2,3.
uint32_t cfgDriveSel1 Drive strength configuration for pins 4,5,6,7.
uint32_t nonSecMask HSIOM non secure mask for port pins 0-7.
uint32_t cfgRes Pull-up resistor configuration for port pins.
uint32_t cfgOut3 Port pin extra drive mode CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ.

◆ cy_stc_gpio_pin_config_t

struct cy_stc_gpio_pin_config_t
Data Fields
uint32_t outVal Pin output state.
uint32_t driveMode Drive mode.
en_hsiom_sel_t hsiom HSIOM selection.
uint32_t intEdge Interrupt Edge type.
uint32_t intMask Interrupt enable mask.
uint32_t vtrip Input buffer voltage trip type.
uint32_t slewRate Output buffer slew rate.
uint32_t driveSel Drive strength.
uint32_t vregEn SIO pair output buffer mode.
uint32_t ibufMode SIO pair input buffer mode.
uint32_t vtripSel SIO pair input buffer trip point.
uint32_t vrefSel SIO pair reference voltage for input buffer trip point.
uint32_t vohSel SIO pair regulated voltage output level.
uint32_t nonSec Secure attribute for each Pin of a port.
uint32_t pullUpRes Pull-up resistor configuration for each pin of a port.