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PSOC E8XXGP Device Support Library
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PSOC E8XXGP Device Support Library
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Data Structures | |
| struct | cy_stc_crypto_rsa_pub_key_t |
| All fields for the context structure are internal. More... | |
| struct | cy_stc_crypto_aes_buffers_t |
| The structure for storing the AES state. More... | |
| struct | cy_stc_crypto_aes_state_t |
| struct | cy_stc_crypto_aes_ccm_buffers_t |
| The structure for storing the AES CCM state. More... | |
| struct | cy_stc_crypto_aes_ccm_state_t |
| struct | cy_stc_crypto_aes_gcm_buffers_t |
| The structure for storing the AES GCM state. More... | |
| struct | cy_stc_crypto_aes_gcm_state_t |
| struct | cy_stc_crypto_sha_state_t |
| The structure for storing the SHA state. More... | |
| struct | cy_stc_crypto_hmac_state_t |
| The structure for storing the HMAC state. More... | |
| struct | cy_stc_crypto_ecc_point |
| A point on a ECC curve. More... | |
| struct | cy_stc_crypto_ecc_key |
| An ECC key. More... | |
| struct | cy_stc_crypto_trng_config_t |
| The structure for storing the TRNG configuration. More... | |
Enumerations | |
| enum | cy_en_crypto_ecc_key_type_t { PK_PUBLIC = 0u , PK_PRIVATE = 1u } |
| An ECC key type. | |
| struct cy_stc_crypto_rsa_pub_key_t |
| struct cy_stc_crypto_aes_buffers_t |
| struct cy_stc_crypto_aes_state_t |
| struct cy_stc_crypto_aes_ccm_buffers_t |
| struct cy_stc_crypto_aes_ccm_state_t |
| struct cy_stc_crypto_aes_gcm_buffers_t |
| struct cy_stc_crypto_aes_gcm_state_t |
| struct cy_stc_crypto_sha_state_t |
| struct cy_stc_crypto_hmac_state_t |
| struct cy_stc_crypto_ecc_point |
| struct cy_stc_crypto_ecc_key |
| struct cy_stc_crypto_trng_config_t |
| Data Fields | ||
|---|---|---|
| uint8_t | sampleClockDiv |
"Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. "clk_sys". "0": sample clock is "clk_sys". "1": sample clock is "clk_sys"/2. "255": sample clock is "clk_sys"/256. |
| uint8_t | reducedClockDiv |
"Specifies the clock divider that is used to produce reduced bits. "0": 1 reduced bit is produced for each sample. "1": 1 reduced bit is produced for each 2 samples. "255": 1 reduced bit is produced for each 256 samples. |
| uint8_t | initDelay |
Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of "3". Field encoding is as follows: "0": 1 sample is dropped. "1": 2 samples are dropped. "255": 256 samples are dropped. The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. |
| bool | vnCorrectorEnable |
"Specifies if the "von Neumann corrector" is disabled or enabled: '0': disabled. '1': enabled. The "von Neumann corrector" post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ("oldest bit, newest bit"): "00": no bit is produced. "01": '0' bit is produced (oldest bit). "10": '1' bit is produced (oldest bit). "11": no bit is produced. Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit). |
| bool | stopOnAPDetect |
Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). |
| bool | stopOnRCDetect |
Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'): '0': Functionality is NOT stopped. '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). |
| bool | ro11Enable | FW sets this field to '1' to enable the ring oscillator with 11 inverters. |
| bool | ro15Enable | FW sets this field to '1' to enable the ring oscillator with 15 inverters. |
| bool | garo15Enable | FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters. |
| bool | garo31Enable |
FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. |
| bool | firo15Enable | FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. |
| bool | firo31Enable |
FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. |
| uint32_t | garo31Poly |
Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. |
| uint32_t | firo31Poly |
Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. |
| cy_en_crypto_trng_bs_sel_t | monBitStreamSelect |
Selection of the bitstream: "0": DAS bitstream. "1": RED bitstream. "2": TR bitstream. "3": Undefined. |
| uint8_t | monCutoffCount8 |
Cutoff count (legal range is [1, 255]): "0": Illegal. "1": 1 repetition. .. "255": 255 repetitions. |
| uint16_t | monCutoffCount16 |
Cutoff count (legal range is [1, 65535]). "0": Illegal. "1": 1 occurrence. ... "65535": 65535 occurrences. |
| uint16_t | monWindowSize |
Window size (minus 1) : "0": 1 bit. ... "65535": 65536 bits. |