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#define | CY_AXIDMAC_INTR_COMPLETION (AXI_DMAC_CH_INTR_COMPLETION_Msk) |
| | Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting.
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#define | CY_AXIDMAC_INTR_SRC_BUS_ERROR (AXI_DMAC_CH_INTR_SRC_BUS_ERROR_Msk) |
| | Bit 1: Bus error for a load from the source.
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#define | CY_AXIDMAC_INTR_DST_BUS_ERROR (AXI_DMAC_CH_INTR_DST_BUS_ERROR_Msk) |
| | Bit 2: Bus error for a store to the destination.
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#define | CY_AXIDMAC_INTR_INVALID_DESCR_TYPE (AXI_DMAC_CH_INTR_INVALID_DESCR_TYPE_Msk) |
| | Bit 3: Invalid descriptor type.
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#define | CY_AXIDMAC_INTR_CURR_PTR_NULL (AXI_DMAC_CH_INTR_CURR_PTR_NULL_Msk) |
| | Bit 5: The channel is enabled and the current descriptor pointer is "0".
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#define | CY_AXIDMAC_INTR_ACTIVE_CH_DISABLED (AXI_DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk) |
| | Bit 6: The channel is disabled and the data transfer engine is busy.
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#define | CY_AXIDMAC_INTR_DESCR_BUS_ERROR (AXI_DMAC_CH_INTR_DESCR_BUS_ERROR_Msk) |
| | Bit 7: Bus error for a load of the descriptor.
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