AXIDMAC (AXI Direct Memory Access Controller)

General Description

Configures the AXIDMA Controller block, channels and descriptors.

The functions and other declarations used in this driver are in cy_axidmac.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

The AXIDMA Controller channel can be used in any project to transfer data without CPU intervention basing on a hardware trigger signal from another component.

The AXIDMA Controller block has a set of registers, a base hardware address, and supports multiple channels. Many API functions for the AXIDMAC driver require a base hardware address and channel number. Ensure that you use the correct hardware address for the AXIDMA Controller block in use.

Features:

• Multiple channels (device specific).
• Four priority levels for each channel.
• Descriptor chaining.
• Configurable source and destination addresses.
• 1D memory copy, 2D memory copy, 3D memory copy descriptor types are supported.
• Configurable input/output triggers and interrupts.

Configuration Considerations

To set up a AXIDMAC driver, initialize a descriptor, initialize and enable a channel, and enable the AXIDMAC block.

To set up a descriptor, provide the configuration parameters for the descriptor in the cy_stc_axidmac_descriptor_config_t structure. Then call the Cy_AXIDMAC_Descriptor_Init function to initialize the descriptor in SRAM. You can modify the source and destination addresses dynamically by calling Cy_AXIDMAC_Descriptor_SetSrcAddress and Cy_AXIDMAC_Descriptor_SetDstAddress.

To set up a AXIDMAC channel, provide a filled cy_stc_axidmac_channel_config_t structure. Call the Cy_AXIDMAC_Channel_Init function, specifying the channel number. Use Cy_AXIDMAC_Channel_Enable to enable the configured AXIDMAC channel.

Call Cy_AXIDMAC_Channel_Enable for each AXIDMAC channel in use.

When configured, another peripheral typically triggers the AXIDMAC channel. The trigger is connected to the AXIDMAC channel using the trigger multiplexer. The trigger multiplexer driver has a software trigger you can use in firmware to trigger the AXIDMAC channel. See the Trigger Multiplexer documentation.

The following is a simplified structure of the AXIDMAC driver API interdependencies in a typical user application:

NOTE: Even if a AXIDMAC channel is enabled, it is not operational until the AXIDMAC block is enabled using function Cy_AXIDMAC_Enable .
NOTE: If the AXIDMAC descriptor is configured to generate an interrupt, the interrupt must be enabled using the Cy_AXIDMAC_Channel_SetInterruptMask function for each AXIDMAC channel. NOTE: When DCache is enabled it is critical to clean the DCache right before calling Cy_AXIDMAC_Channel_Enable .Cleaning the cache too early or too late may result in a CY_AXIDMAC_INTR_SRC_BUS_ERROR interrupt.
Ensure cache maintenance operations are performed at the correct point in the sequence to avoid data coherency issues.

Scenario: AXIDMAC with DMA descriptors, DMA config descriptors, source and destination buffer stored in memory other then DTCM(CM55 private MEMORY) such as SOCMEM or FLASH

  #define AXIDMAC_DESCRIPTOR CY_SECTION(".cy_socmem_data") cy_stc_axidmac_descriptor_t
  /* Scenario: Initialize a 2D descriptor with descriptors, src and dst are in SOCMEM*/
  #define DATACNT (8UL)
  CY_SECTION(".cy_socmem_data") cy_stc_axidmac_descriptor_t firstDescriptor;
  CY_SECTION(".cy_socmem_data") cy_stc_axidmac_descriptor_t nextDescriptor;
  CY_SECTION(".cy_socmem_data") uint32_t src[DATACNT];
  CY_SECTION(".cy_socmem_data") uint32_t dst[DATACNT];
  CY_SECTION(".cy_socmem_data") cy_stc_axidmac_descriptor_config_t descriptor_cfg =
  {
        .retrigger = CY_AXIDMAC_RETRIG_IM,
        .interruptType = CY_AXIDMAC_DESCR,
        .triggerOutType = CY_AXIDMAC_DESCR,
        .channelState = CY_AXIDMAC_CHANNEL_ENABLED,
        .triggerInType = CY_AXIDMAC_DESCR,
        .descriptorType = CY_AXIDMAC_2D_MEMORY_COPY,
        .srcAddress = &src,
        .dstAddress = &dst,
        .mCount=1U,
        .srcXincrement = 1U,
        .dstXincrement = 1U,
        .xCount = DATACNT,
        .srcYincrement = 0U,
        .dstYincrement = 0U,
        .yCount = 1UL,
        .nextDescriptor = &nextDescriptor,
  };
 
void snippet_Cy_AXIDMAC_Enable(void)
{
  /* Scenario: Setup and enable the AXIDMAC channel 0 */
    cy_stc_axidmac_channel_config_t channelConfig;
    channelConfig.enable = false;
    channelConfig.bufferable = false;
    channelConfig.descriptor = &firstDescriptor;
    if (CY_AXIDMAC_SUCCESS != Cy_AXIDMAC_Descriptor_Init(&firstDescriptor, &descriptor_cfg))
    {
        /* Insert error handling */
    }
 
    if (CY_AXIDMAC_SUCCESS != Cy_AXIDMAC_Channel_Init(SAXI_DMAC, 0UL, &channelConfig))
    {
        /* Insert error handling */
    }
 
    Cy_AXIDMAC_Channel_SetDescriptor(SAXI_DMAC, 0UL, &firstDescriptor);
    Cy_AXIDMAC_Channel_SetPriority(SAXI_DMAC, 0UL, 3UL);
    Cy_AXIDMAC_Channel_Enable(SAXI_DMAC, 0UL);
    Cy_AXIDMAC_Enable(SAXI_DMAC);
 
}

Scenario: AXIDMAC with DMA descriptors, DMA config descriptors, source and destination buffer stored in DTCM memory (CM55 private MEMORY), in this case address need to be remap to external master mapped address

 
    /* Scenario: Initialize a 2D descriptor */
    #define DATACNT (8UL)
    /* Scenario: src, dst and descriptors are in default Data section
    which will go in CM55 DTCM memory */
    cy_stc_axidmac_descriptor_t firstDescriptor_local;
    cy_stc_axidmac_descriptor_t nextDescriptor_local;
    uint32_t src_data[DATACNT];
    uint32_t dst_data[DATACNT];
 
    cy_stc_axidmac_descriptor_config_t descriptor_cfg_local =
    {
        .retrigger = CY_AXIDMAC_RETRIG_IM,
        .interruptType = CY_AXIDMAC_DESCR,
        .triggerOutType = CY_AXIDMAC_DESCR,
        .channelState = CY_AXIDMAC_CHANNEL_ENABLED,
        .triggerInType = CY_AXIDMAC_DESCR,
        .descriptorType = CY_AXIDMAC_2D_MEMORY_COPY,
        .srcAddress = &src_data,
        .dstAddress = &dst_data,
        .mCount=1U,
        .srcXincrement = 1U,
        .dstXincrement = 1U,
        .xCount = DATACNT,
        .srcYincrement = 0U,
        .dstYincrement = 0U,
        .yCount = 1UL,
        .nextDescriptor = &nextDescriptor_local,
    };
     /* Descriptor address need to be remap */
    descriptor_cfg_local.nextDescriptor = (cy_stc_axidmac_descriptor_t *)(cy_DTCMRemapAddr)(&nextDescriptor_local);
 
    if (CY_AXIDMAC_SUCCESS != Cy_AXIDMAC_Descriptor_Init(&firstDescriptor_local, &descriptor_cfg_local))
    {
        /* Insert error handling */
    }
 
    /* remapping src and dst DTCM address */
    Cy_AXIDMAC_Descriptor_SetSrcAddress(&firstDescriptor_local, (void const *)src_data);
    Cy_AXIDMAC_Descriptor_SetDstAddress(&firstDescriptor_local, (void const *)dst_data);
 
    /* Scenario: Setup and enable the AXIDMAC channel 0 */
    cy_stc_axidmac_channel_config_t channelConfig;
    channelConfig.enable = false;
    channelConfig.bufferable = false;
    channelConfig.descriptor = &firstDescriptor_local;
 
    /* remapping channel descriptor address */
    channelConfig.descriptor = (cy_stc_axidmac_descriptor_t *)(cy_DTCMRemapAddr(&firstDescriptor_local));
 
    if (CY_AXIDMAC_SUCCESS != Cy_AXIDMAC_Channel_Init(SAXI_DMAC, 0UL, &channelConfig))
    {
        /* Insert error handling */
    }
 
    Cy_AXIDMAC_Channel_SetDescriptor(SAXI_DMAC, 0UL, &firstDescriptor_local);
    Cy_AXIDMAC_Channel_SetPriority(SAXI_DMAC, 0UL, 3UL);
    Cy_AXIDMAC_Channel_Enable(SAXI_DMAC, 0UL);
 
    Cy_AXIDMAC_Enable(SAXI_DMAC);
 

More Information.

See the AXIDMAC chapter of the device technical reference manual (TRM).

API Reference
	Macros
	Interrupt Masks
	Functions
	Data Structures
	Enumerated Types