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#define | CY_AUTANALOG_FIFO_BUFS_NUM (8UL) |
| | The maximum number of FIFO buffers.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW0 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW0_INT_Msk) |
| | FIFO LEVEL 0 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW1 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW1_INT_Msk) |
| | FIFO LEVEL 1 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW2 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW2_INT_Msk) |
| | FIFO LEVEL 2 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW3 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW3_INT_Msk) |
| | FIFO LEVEL 3 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW4 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW4_INT_Msk) |
| | FIFO LEVEL 4 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW5 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW5_INT_Msk) |
| | FIFO LEVEL 5 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW6 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW6_INT_Msk) |
| | FIFO LEVEL 6 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_OVERFLOW7 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW7_INT_Msk) |
| | FIFO LEVEL 7 overflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL0 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL0_INT_Msk) |
| | FIFO LEVEL 0 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL1 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL1_INT_Msk) |
| | FIFO LEVEL 1 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL2 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL2_INT_Msk) |
| | FIFO LEVEL 2 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL3 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL3_INT_Msk) |
| | FIFO LEVEL 3 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL4 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL4_INT_Msk) |
| | FIFO LEVEL 4 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL5 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL5_INT_Msk) |
| | FIFO LEVEL 5 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL6 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL6_INT_Msk) |
| | FIFO LEVEL 6 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_LEVEL7 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL7_INT_Msk) |
| | FIFO LEVEL 7 cause interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW0 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW0_INT_Msk) |
| | FIFO LEVEL 0 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW1 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW1_INT_Msk) |
| | FIFO LEVEL 1 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW2 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW2_INT_Msk) |
| | FIFO LEVEL 2 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW3 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW3_INT_Msk) |
| | FIFO LEVEL 3 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW4 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW4_INT_Msk) |
| | FIFO LEVEL 4 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW5 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW5_INT_Msk) |
| | FIFO LEVEL 5 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW6 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW6_INT_Msk) |
| | FIFO LEVEL 6 underflow interrupt mask.
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#define | CY_AUTANALOG_INT_FIFO_UNDERFLOW7 (LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW7_INT_Msk) |
| | FIFO LEVEL 7 underflow interrupt mask.
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